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Recent content by First Strike

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    Intel Looks Beyond CMOS to the Future of Logic Devices

    As for cluster computing, the trend is quite clear, use electronics to do the computing and use silicon photonics to do the communication. Reality: silicon photonics is used as a discrete I/O device communicating between nodes. Almost reality: on-chip photonics for chip-to-chip communication...
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    Intel Looks Beyond CMOS to the Future of Logic Devices

    current CMOS technology: characteristic width 7nm~14nm, futher shrink down possible Silicon photonics: waveguide width: ~500nm, clearance around waveguide: 1um, typical modulator length: a few mm, impossible to shrink due to Maxwell eq. Optical fiber: diameter: a few um It is because of size.
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    Intel Readies "KF" Variants of Key 9th Gen Core Desktop SKUs

    There is almost zero possibility that the iGPU will be physically absent. It would be crazy for Intel to introduce three new die variant for (a generation that is going to be dropped in half a year) and (a process node which is going to be dropped in a year or so) on top of four existing MSDT...
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    AMD Doubles L3 Cache Per CCX with Zen 2 "Rome"

    So Rome comes with 256MB L3 cache? not the previously rumored 128MB L3? This is getting increasingly interesting, in the aspect of cache hierarchy. 256MB L3 = definitely no L4 as LLC on the IO chip, because IO chip definitely is not large enough to cram in 512MB L4. So how will they arrange and...
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    AMD Zen 2 "Rome" MCM Pictured Up Close

    Judging from the die size, I'd say there is a high probability that L3 cache is present on individual CPU chiplet. Despite that AMD didn't clarify its FPU architecture, THIS IS F**KING AWESOME. Threadripper 3000s will be perfect for HPC.
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    Intel Announces Cascade Lake Advanced Performance and Xeon E-2100

    Such HPC marks can be way dirtier. Like the choice of block size in LINPACK. I can say with certainty that this block size is optimal or near-optimal for CSL-AP with MKL. And EPYC with BLIS would probably have a different performance-to-block-size curve.
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    Intel Announces Cascade Lake Advanced Performance and Xeon E-2100

    Hey, counting threads in HPC workload is not an advisable move. SMT can hinder HPC performance according to some. And what's wrong with this 3.4x anyway? Skylake-SP has two AVX-512 execution unit per core and zen1 has two 128-bit ADD and two 128-bit MUL instead. No surprise a crushing advantage...
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    Intel Announces Cascade Lake Advanced Performance and Xeon E-2100

    Doesn't SMT worsen Linpack performances? I've seen a lot of suggestions of turning off SMT when doing HPC.
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    Editorial Apple's A12X Shows Us How The ARM MacBook Is Closer Than Ever

    Yea yea yea, I know A12&A11's big core has a extravagant configuration comparable to Intel's counterpart. But would someone please provide some data other than the infamous Geekbench. Personally, I welcome this change, because I think this is what ultrabook should do. But it will seriously...
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    AMD Could Solve Memory Bottlenecks of its MCM CPUs by Disintegrating the Northbridge

    The only question now is whether the 32MB L3 cache per CCX chip will be present as this leak suggests. It is totally possible that L3 cache all get dumped to the center controller chip. 32MB cache in 7nm is really some cost to consider. And making 8 of them shared and coherent is hard AF. If...
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    Darren McPhee, Former Radeon Marketing Executive, Joins Intel's Discrete Graphics Division

    Even Intel didn't do such crap like advertising "EPIC Failure". Intel's PR are nuts, but at best they just manipulate reviews and advertising their monolithic crap. They don't troll.
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    NVIDIA's GDDR5X-varnished GTX 1060 Only Ticks at 8.8 Gbps Over 192-bit

    I didn't expect that Micron produced so much defects.
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    Intel Increases L1D and L2 Cache Sizes with "Ice Lake"

    Nope... Cache is still a must. No matter how fast the memory/IO may be, internal CPU pipelines will always be way faster. I agree with your opinion. Only that SKL-SP's victim cache is not necessarily more efficient. The efficiency of a victim cache and an inclusive cache depends on the...
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    Intel Could Have Killed 10 nm Process According to SemiAccurate Report [Updated]

    Yes, I mean the same. The TDP has almost no indication of actual power consumption. Yet Mr. Demerjian infered (rather than tested) i3-8121U's power consumption by merely looking at the TDP data from Intel ARK. And even more, they even do some math like 25W/2=12.5W on some CFL-R chips, assuming...
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    Intel Could Have Killed 10 nm Process According to SemiAccurate Report [Updated]

    Well I don't know how you think about the source. But after reading 2 articles from Mr. Demerjian @ SemiAccurate, specifically the two linked in your article, I think they are trolls, and very bad trolls. A crank and narcissist in my opinion. They infer i3-8121U's power consumption from...
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