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AMD Readies X370 High-end Chipset for "Summit Ridge" Processors

btarunr

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AMD is readying three motherboard chipsets for its next-generation socket AM4 desktop platform. With its 7th generation A-series "Bristol Ridge" APUs, the company launched the A320 mainstream and B350 premium motherboard chipsets, while keeping a better-endowed high-end chipset under the wraps, which makes its debut with the ZEN "Summit Ridge" processors. It turns out that this chipset is the AMD X370. The X370 chipset will debut with the first ZEN "Summit Ridge" processors along the sidelines of the 2017 International CES, next January.

AMD "Summit Ridge" desktop processors, much like the 7th generation A-series APUs they share the platform with, are SoCs, in that the chips combine the entire platform core-logic along with the CPU and its relevant uncore components. AMD is still giving this platform a sort of chipset, which adds to the number of SATA, USB, and general-purpose PCI-Express connectivity that the processor gives out. The AMD X370 should feature more 10 Gb/s USB 3.1 ports, SATA 6 Gb/s ports, 32 Gb/s M.2 or U.2 ports, and general-purpose PCIe lanes than what the B350 offers. This chipset should drive motherboards that are ready for multi-GPU setups.



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I can wait, nothing will change much on the computer side of things between now and then anyway.
 
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I'm confused here. Is "Zen" now the brand name, similar to "Athlon" or "FX", or is that still unknown?
 
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I like their naming scheme. AMD ZEN X370 sounds really cool, isn't too long and is easy to remember. Good choice AMD.
 
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w8 wut??
X370 is a flagship MOTHERBOARD CHIPSET for Zen, not the CPU itself!
 
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I'm confused here. Is "Zen" now the brand name, similar to "Athlon" or "FX", or is that still unknown?

No, its the architecture name, like Bulldozer or Piledriver.
 
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"Each CCU houses four CPU cores with 512 KB of dedicated L2 cache, and 8 MB of shared L3 cache. The total cache (L2 + L3) for the ZEN X370, hence, is 20 MB."

I may fail at math sometimes, but there seems to be something wrong here.
For me, (0.5+8)x2=17, not 20...
 

btarunr

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I grossly misread the Expreview article. I've since rewritten the entire article. Sorry.
 
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"Each CCU houses four CPU cores with 512 KB of dedicated L2 cache, and 8 MB of shared L3 cache. The total cache (L2 + L3) for the ZEN X370, hence, is 20 MB."

I may fail at math sometimes, but there seems to be something wrong here.
For me, (0.5+8)x2=17, not 20...

it IS 20MB

(512kB*4 + 8MB)*2 = 20MB
 
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"Each CCU houses four CPU cores with 512 KB of dedicated L2 cache, and 8 MB of shared L3 cache. The total cache (L2 + L3) for the ZEN X370, hence, is 20 MB."

I may fail at math sometimes, but there seems to be something wrong here.
For me, (0.5+8)x2=17, not 20...
((0.5x4)+8)x2
 
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"Each CCU houses four CPU cores with 512 KB of dedicated L2 cache, and 8 MB of shared L3 cache. The total cache (L2 + L3) for the ZEN X370, hence, is 20 MB."

I may fail at math sometimes, but there seems to be something wrong here.
For me, (0.5+8)x2=17, not 20...

Each CCU has four cores, each core has 512KB, each CCU has 8MB.

2 CCUs = 2x8MB + 8x512KB = 20MB

It is correct just badly worded.
 

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I don't like how closely their naming system matches Intel. Like...almost identical. Come on AMD, you can do better!
 

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will they overclock?
 

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"Each CCU houses four CPU cores with 512 KB of dedicated L2 cache, and 8 MB of shared L3 cache. The total cache (L2 + L3) for the ZEN X370, hence, is 20 MB."

I may fail at math sometimes, but there seems to be something wrong here.
For me, (0.5+8)x2=17, not 20...

Pretty sure its 512KB of L2 per core , hence the 20MB.
 
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Isn't L3 shared across all CCUs, so it's really 12MB of cache ?
 
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I don't like how closely their naming system matches Intel. Like...almost identical. Come on AMD, you can do better!

....was just thinking Intel will probably be on their Z270 chipset and whooomp!!!!! Amd comes out with the X370.... marketing at its best.... Anyway tired of hearing about it, want to see it and some numbers....
 
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Well it says each CCU has 8MB of L3 /shrug
Looking at the older slides, it seems that each 4 core cluster does indeed have its own l3 cache.
 
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Any speculation regarding the tdp of such chipset? Hopefully below 4W



edit:
Source
 
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People keep saying MB chipset....there is no MB chipset, right? It's all on die, no?
 
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