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Editorial Moore's Law - Is it Really Dead ?

ppn

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You have the transistor count flipped.
The scaling is 80.7% (not 1.66x or 66%)
You can't compare process nodes across different foundries. Polaris was produced by Glofo, Navi is produced by TSMC. The "nm" name given to an individual process node is largely a marketing term meant to indicate progress, not representative of a linear shrink compared to a prior node.

Polaris was first made by TSMC. transistors increase 5700 to 10300. die size 232 to 251. Density is up 1,67, transistor count 1,80. More transistors, bigger chip. Took them 3 years exactly. Nothing is flipped. tsmc samsung and glofo shows similar calculated density of their 12-14-16 if we take similar products 1050ti samsung,1060 tsmc and rx 480 tsmc, 580 glofo for example. Of course on paper density is much higher. Given that 14 nm is 33 on paper and 25 Mtr 5700/232. 7 nm is 90-100 Mtr per sq.mm on paper or 3 times that of 14nm and only 41 Mtr calculated 10300/251. It is obvious that 5nm may not even be able to provide a final product that could reach 67% scaling in 2 years despite being 171 Mtr.sq.mm.
 
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It is taking a bit longer than 18 months, or even 2 years, for the number of transistors on a mainstream die to double. So Moore's Law is not quite what it was, but the number of transistors on a chip is still increasing at a pace that is only a little slower, and, yes, there is still some room to go before the size of atoms limits how feature size can shrink. Of course, the number of transistors can also be increased by allowing die sizes to grow, too. But Dennard Scaling, on the other hand, has definitely come to an end; that's why we don't have 8 GHz microprocessors these days.

So the landscape has changed, and it is continuing to change. But there are still ways to provide more powerful computers that will remain open for some time to come.
 
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It is taking a bit longer than 18 months, or even 2 years, for the number of transistors on a mainstream die to double. So Moore's Law is not quite what it was
This has been my observation as well.
but the number of transistors on a chip is still increasing at a pace that is only a little slower, and, yes, there is still some room to go before the size of atoms limits how feature size can shrink.
This is only part of the problem. Silicon as a semi-conductor substrate material is reaching the end of how far it can be reduced while still maintaining acceptable functional voltage. Silicon/Arsenic blend is being experimented with, but Silicon/Tellurium blend seems more promising from a electrochemical perspective. Additionally, moving away from transistor based technology to trisistors or quadsistors is the next logical step. This will require creating new computer math(trinary or quadnary instead of binary) and new software, or at the very least adapting binary software to work on trinary/quadnary hardware.
 
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Ternary computing isn't actually a new thing. There were working ternary computers in the Soviet Union in the 50s or 60s.
 
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Ternary computing isn't actually a new thing. There were working ternary computers in the Soviet Union in the 50s or 60s.
Not Ternary(as in Ternary Operation, the mathematical function), Trinary, as in three bits per transistive element, 1 "off" state and 2 distinctive "on" states. Quadnary is similar, 1 "off" state and 3 distinctive "on" states.
 
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Not sure. Probably just the circumstances of the time.
 
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Not sure. Probably just the circumstances of the time.

Yea the old war caused a lot of Tech to be developed either in parallel or in completely different ways. NAND Flash uses 8 states if I remember correctly.

Binary software should be easy to emulate on a quadnary or trinary system if you just use the first 2 states. It would really cause a huge speed up only needing to move 1/2+1 times as many bits around. There are already trigate transistors you would essentially need dual drain and dual gate transistors. if you had 2 drains in parallel it would divide the current depending on how many of them the current flows through. You would have off, full I, half I. Then by having 2 gates you can turn half the gate on or the entire gate so the current flows through 1 or both drains.
 
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