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- Feb 3, 2017
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Processor | R5 5600X |
---|---|
Motherboard | ASUS ROG STRIX B550-I GAMING |
Cooling | Alpenföhn Black Ridge |
Memory | 2*16GB DDR4-2666 VLP @3800 |
Video Card(s) | EVGA Geforce RTX 3080 XC3 |
Storage | 1TB Samsung 970 Pro, 2TB Intel 660p |
Display(s) | ASUS PG279Q, Eizo EV2736W |
Case | Dan Cases A4-SFX |
Power Supply | Corsair SF600 |
Mouse | Corsair Ironclaw Wireless RGB |
Keyboard | Corsair K60 |
VR HMD | HTC Vive |
No. Remember that this is a packaging thing. You can use it to route any traces or connection over it. For example, AMD could route IF over EMIB faster and more power efficiently than current CPU packaging. TSMC is developing similar solutions so that might/will come to pass at one point.was that developed for core+vega apus only ? seems wasteful.
It is likely that APUs with Vega were a kind of mass-production test of sorts. In these APUS, EMIB was used for GPU-HBM connection, meaning connecting the very wide memory bus from GPU to HBM without having a full interposer.