Intel's Sapphire Rapids Xeons to Feature up to 64 GB of HBM2e Memory

[AleksandarK]

During the Supercomputing (SC) 21 event, Intel has disclosed additional information regarding the company's upcoming Xeon server processor lineup, codenamed Sapphire Rapids. One of the central areas of improvement for the new processor generation is the core architecture based on Golden Cove, the same core found in Alder Lake processors for consumers. However, the only difference between the Golden Cove variant found in Alder Lake and Sapphire Rapids is the amount of L2 (level two) cache. With Alder Lake, Intel equipped each core with 1.25 MB of its L2 cache. However, with Sapphire Rapids, each core receives a 2 MB bank.

One of the most exciting things about the processors, confirmed by Intel today, is the inclusion of High-Bandwidth Memory (HBM). These processors operate with eight memory channels carrying DDR5 memory and offer PCIe Gen5 IO expansion. Intel has confirmed that Sapphire Rapids Xeons will feature up to 64 GB of HBM2E memory, including a few operating modes. The first is a simple HBM caching mode, where the HBM memory acts as a buffer for the installed DDR5. This method is transparent to software and allows easy usage. The second method is Flat Mode, which means that both DDR5 and HBM are used as contiguous address spaces. And finally, there exists an HBM-only mode that utilizes the HBM2E modules as the only system memory, and applications fit inside it. This has numerous benefits, primarily drawn from HBM's performance and reduced latency.


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[Arrakis9]

Would be interesting to see a cpu running an os with no ram installed...

 

[londiste]

Would be interesting to see a cpu running an os with no ram installed...

RAM? At size like 64GB, it would not need storage either

 

[AleksandarK]

RAM? At size like 64GB, it would not need storage either

Fujitsu A64FX, that powers Fugaku supercomputer, uses 32 GB of HBM as well, and IIRC only uses this for RAM. It has no problems being the fastest pre-exascale supercomputer for now

 

[ratirt]

I think this HBM mem in general has a very cool implementations. It would have helped a lot in some cases. Too bad it is quite expensive but maybe it will change?

 

[Punkenjoy]

I am curious how the cache mode will perform. it it's too granular, it might require too much processing power to operate. I suspect they will just cache large chunk of main memory.

For the contiguous, I wonder if it will be shown as NUMA or UMA.

I hope the HBMe only version is a low core count because else, it will be so much memory starved.

 

[Rob94hawk]

Does the memory speed match the cpu? That's what I would like to know. This could put RAM companies out of business if this becomes the norm.

 

[MentalAcetylide]

Does the memory speed match the cpu? That's what I would like to know. This could put RAM companies out of business if this becomes the norm.

I wouldn't expect something like this to become available for your average or even high-end desktops any time soon, so I think the future of companies producing RAM is still secure and will be so for quite some time.

 

[Rob94hawk]

I wouldn't expect something like this to become available for your average or even high-end desktops any time soon, so I think the future of companies producing RAM is still secure and will be so for quite some time.

True. However this might be highly beneficial for AMD who's current cpu's are picky about what RAM you are using.

 

[ScaLibBDP]

The HBM2e technology that Intel uses on Intel Sapphire Rapids Xeon CPUs is Not new and was "borrowed"
from Intel Knights Landing ( KNL ) Xeon Phi architecture.

On Intel KNL-series CPUs it was called as MCDRAM and here are core features of these CPUs:

Code name: Knights Landing ( KNL )
Process technology: 14nm
On-Package Memory: High Bandwidth MCDRAM ( up to 16GB / bandwidth >400GB/s )
Regular Memory: DDR4 ( up to 384GB / bandwidth > 80GB/s )
Instruction Set Architecture: Intel AVX-512 ( vector length 512-bit )

Supports Memory modes of MCDRAM:
- Cache
- Flat
- Hybrid
- MCDRAM only

Supports Cluster modes:
- All2All
- SNC-2
- SNC-4
- Hemisphere
- Quadrant

I've worked with an Intel KNL-server with Xeon Phi Processor 7210 CPU:

https://ark.intel.com/products/94033/Intel-Xeon-Phi-Processor-7210-16GB-1_30-GHz-64-core

Intel Xeon Phi Processor 7210 ( 16GB, 1.30 GHz, 64 core )
Cores : 64
Processors ( CPUs ) : 256
Threads per core : 4
Peak Processing Power: 2.662 TFLOPs ( Single Precision )

In order to see how Memory- and Cluster-modes worked in "action" take a look at these
two Video Technical Reports ( VTRs ):

Strassen Matrix Multiplication algorithms on Intel KNL Server ( VTR-112 )

( Video Slides 12, 23, 33, 34, 42 and 50 )

Performance of Classic Matrix Multiplication algorithm on a Server System ( VTR-048 )

( Video Slides 25, 28, 29, 32, 33, 34 and 35 )

>>...For the contiguous, I wonder if it will be shown as NUMA...

It supports NUMA.