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    Intel "Raptor Lake" is a 24-core (8 Big + 16 Little) Processor

    Yes, auto vectorization does not do much, but they do carry around 3% improvement in most packages (I remember seeing that figure from some Gentoo compilation tests). That's something for free still.
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    Intel "Raptor Lake" is a 24-core (8 Big + 16 Little) Processor

    AVX is not something rare. It can be auto-generated by the compiler. If you ever turn on -O3 optimization flag (which includes -ftree-loop-vectorize option) in GCC, then you get auto vectorization for all eligible loops in your code. If you write simple loops, they will be transformed in to...
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    Chinese Manufacturer Asgard to Launch DDR5 128 GB, 5,600 MHz Sticks As Early as 2022

    JEDEC is not a government entity like US FDA or FCC. JEDEC is a board of memory manufacturers, CPU/MCU manufacturers, mobo manufacturers, and server manufacturers. They empower JEDEC not the reverse. If they don't settle on some agreement, they there won't be a JEDEC standard to begin with...
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    AMD Zen 5 "Strix Point" Processors Rumored To Feature big.LITTLE Core Design

    x64 and ARMv8 doesn't even have the same memory order model. They have ZERO possibility of inter-core communication. Since they are fundamentally not co-existable, why not solder an extra Raspberry chip on your board?
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    Chinese Manufacturer Asgard to Launch DDR5 128 GB, 5,600 MHz Sticks As Early as 2022

    You are mixing cause and effect. A spec is a temporary compromise between manufacturers. The spec are so shitty because they can only make these shitty timings at presumed launch time. Not they make shitty timings because of the spec.
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    Netac Kickstarts Research and Development Process for 10 GHz DDR5 Memory

    Not so funny when you actually search for the first patent for USB flash drive. Someone can even claim to have invented integrated circuits because of his own personal diary. (Not speaking ill of Noyce anyway)
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    Rumor: AMD Ryzen 7000 (Raphael) to Introduce Integrated GPU in Full Processor Lineup

    Why would someone do that? You can't seriously expect every floating point arithmetic to be offload to GPU and cause CPU pipeline to stall for 1000+ cycles? fpu in CPU is for the low-latency operations within the out-of-order pipeline, GPU not relevant in this context. Even something like AVX...
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    AMD Ryzen 5000 Series CPUs with Zen 3 Cores Could be Vulnerable to Spectre-Like Exploit

    No they don't. Short version: to find a bug is a non-computable problem. Long version: All security/correctness properties can only be proven under an assumption, and only works under that assumption, e.g., eventual correctness of execution result, etc. "Side channel attacks" just means they...
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    Manufacturing: Samsung Semiconductor Fabs in Texas Shut Down Following State-wide Power Shortages

    First law of physics: Nobody sends uncompressed gas. If you compress a gas with 200-1500 psi pressure, then they will surely freeze in a much higher tempereture. Ethane for example, turns into liquid around merely -10 F at 200 psi, as opposed to -127 F in normal pressure. If you choose a heavy...
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    Pat Gelsinger: "Intel Has to be Better at Making CPUs Than That Lifestyle Company"

    You must be completely new to semi process to do such an "equivalent" transformation. As always, it's a bad habit to think you've mastered something by scrapping through online forums. I/O barely shrinks with process, and I/O alone is taking up a good part of modern SoC. Your 1.84x density only...
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    Pat Gelsinger: "Intel Has to be Better at Making CPUs Than That Lifestyle Company"

    1. M1 measures at 119 mm2, 4800U measures at 156 mm2. 156 is not smaller than 119. 2. 4800U does not beat M1 in most single-threaded load. Unless you use x86 emulation. 3. M1's GPU trashes Renoir's. It's just an overkill. 4. Renoir also got 45W H-variant. But it doesn't help. Conclusion: which...
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    Linus Torvalds Calls Out Intel for ECC Memory Market Stagnation

    The bit flip is seen only when you can see it. Most of the time bit flip doesn't cause immediate crash thanks to software engineering but that doesn't mean it won't cause problems. In a non-ECC environment, you will find a heavy floating number calculation program to produce slightly different...
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    GPUs to See Price Increase Due to Import Tariffs, Other PC Components to Follow

    You are the first one in this post to realize the problem. The wage is only a small part of it. The large part is that China has attracted the entire manufacturing chain into its industrial complexes over the years. Sure you can move the PCB fab to, say, Arizona. But where to buy suitable...
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    EU Signs Declaration for 2 nm Node and Custom Processor Development

    Come on, don't be so sour in this thread. IMO, they might have some decent progress in the end. Look at SMIC in China. They got ~10 Billion USD government investment in past few years and they marched from 28nm to their 7nm (Slightly denser than TSMC's 10nm). And that is achieved under the...
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    A Christmas Miracle: 500,000 NVIDIA RTX 3080 Cards Found in Lost Shipping Container

    Samsung has no AIB business. The only thing they ship with a NVIDIA logo are chips (such as GA104 etc.), not cards. So I say they somehow came up with a really realistic number for a fictional story.
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    Intel Expands 10nm Manufacturing Capacity

    Great, now self-taught, mobile-learning geniuses are expanding their business from election to semiconductor industries. I thought you were referring to GloFo's 7nm PR-ish nonsense a few years ago. Aside from that, GloFo was okay. The writing was on the wall and GloFo went with reality in the end.
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    MATLAB MKL Codepath Tweak Boosts AMD Ryzen MKL Performance Significantly

    This is a modification that you are really risking your own lives. You know, within one update Intel can make some modifications that "unintentionally" cause numerical bugs on some user-modified systems. There may well be some already.
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    Thermalright Rolls Out AXP-90 Full Copper CPU Cooler

    I think this is a much better heatpipe design than Cryorig C7. C7's heat pipe bending cut off a tremendous amount of fin area from heatpipe connectivity, right at the area of strongest airflow. I'll wait and see the performance of this cooler
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    AMD Zen 2 has Hardware Mitigation for Spectre V4

    This post contains horribly outdated information about Intel. Intel already resolved Spectre V4 with a new stepping for months. https://www.intel.com/content/www/us/en/architecture-and-technology/engineering-new-protections-into-hardware.html Yet Techpowerup seems to be unaware.
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    Intel Looks Beyond CMOS to the Future of Logic Devices

    As for cluster computing, the trend is quite clear, use electronics to do the computing and use silicon photonics to do the communication. Reality: silicon photonics is used as a discrete I/O device communicating between nodes. Almost reality: on-chip photonics for chip-to-chip communication...
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    Intel Looks Beyond CMOS to the Future of Logic Devices

    current CMOS technology: characteristic width 7nm~14nm, futher shrink down possible Silicon photonics: waveguide width: ~500nm, clearance around waveguide: 1um, typical modulator length: a few mm, impossible to shrink due to Maxwell eq. Optical fiber: diameter: a few um It is because of size.
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    Intel Readies "KF" Variants of Key 9th Gen Core Desktop SKUs

    There is almost zero possibility that the iGPU will be physically absent. It would be crazy for Intel to introduce three new die variant for (a generation that is going to be dropped in half a year) and (a process node which is going to be dropped in a year or so) on top of four existing MSDT...
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    AMD Doubles L3 Cache Per CCX with Zen 2 "Rome"

    So Rome comes with 256MB L3 cache? not the previously rumored 128MB L3? This is getting increasingly interesting, in the aspect of cache hierarchy. 256MB L3 = definitely no L4 as LLC on the IO chip, because IO chip definitely is not large enough to cram in 512MB L4. So how will they arrange and...
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    AMD Zen 2 "Rome" MCM Pictured Up Close

    Judging from the die size, I'd say there is a high probability that L3 cache is present on individual CPU chiplet. Despite that AMD didn't clarify its FPU architecture, THIS IS F**KING AWESOME. Threadripper 3000s will be perfect for HPC.
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    Intel Announces Cascade Lake Advanced Performance and Xeon E-2100

    Such HPC marks can be way dirtier. Like the choice of block size in LINPACK. I can say with certainty that this block size is optimal or near-optimal for CSL-AP with MKL. And EPYC with BLIS would probably have a different performance-to-block-size curve.
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