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AMD Confirms Zen 5 will Get Ryzen 8000 Series Branding, "Navi 3.5" Graphics in 2024

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I wonder why AMD doesn't make the CPU as 8 Zen5 VCache cores + 16 Zen5c/4c cores.

Why not compete with Intel that way? They can still offer 16 full zen5 core CPUs and it would greatly differentiate the VCache variants from the regular.
The number of cores matters less. Addressable threads matter more in many workloads. 16C/32T 7950X is as good in MT workloads as 24C/32T 13900K is, and Ryzen uses less power in those workloads.

7700X is 8C/16T. It competes against 13600K with 14C/20T. It has 6 cores less, but it is only 5% slower in MT workloads. 6 cores less for 5% less! Do you get the vibe?
Performance Intel ADL RPL Zen4 Zen3 3D centre.png

But that is also my point though, instead they should mix big zen vcache cores with little C cores so that the windows scheduler can more easily separate them just like they already do with Intel.
Big cores+c cores+V cache is more complex combination that they are testing in labs. You will need to be patient for that.
Once AMD first releases vanilla big cores+c cores, Windows scheduler will not have any problems, as c cores have the same instructions and HT, just less L1/L2/L3 memory. Those are simply smaller cores, but different than Intel's little cores. AMD's big and c cores both support HT and AVX512. So, 8+8 SKU will have 32 threads, unlike Intel's 24 threads on 8+8 cores. AMD did not want to go Intel's way with c cores and make them single-threaded because this creates more problems with execution of instructions. That's why Intel cancelled AVX512 on consumer big-little CPUs. AMD's version of efficient c-cores will be far more capable in MT workloads than little cores
Sure but AMD is sitting on this "c" type core technology since 2 gens now and is not doing anything on the client segment with it. Intel is about to bring 8+32 cores to the market and AMD will remain with just 16 big cores which won't win either the single or the multi threaded benches. It will just be more energy efficient. I would like to see a 8 + 16 from AMD at some point.
Which two generations? Nonsense. The first SKU with c-cores will be Bergamo with 128 c cores, to be released this summer. The CPU is already in test systems of hyperscalers. It's the first ever product with 16-core chiplets, each with 8 core CCX.

Most advanced and complex technologies usually come to server space that needs it, and later trickle down consumer segment.
 
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The number of cores matters less. Addressable threads matter more in many workloads. 16C/32T 7950X is as good in MT workloads as 24C/32T 13900K is, and Ryzen uses less power in those workloads.

7700X is 8C/16T. It competes against 13600K with 14C/20T. It has 6 cores less, but it is only 5% slower in MT workloads. 6 cores less for 5% less! Do you get the vibe?
View attachment 299617

Big cores+c cores+V cache is more complex combination that they are testing in labs. You will need to be patient for that.
Once AMD first releases vanilla big cores+c cores, Windows scheduler will not have any problems, as c cores have the same instructions and HT, just less L1/L2/L3 memory. Those are simply smaller cores, but different than Intel's little cores. AMD's big and c cores both support HT and AVX512. So, 8+8 SKU will have 32 threads, unlike Intel's 24 threads on 8+8 cores. AMD did not want to go Intel's way with c cores and make them single-threaded because this creates more problems with execution of instructions. That's why Intel cancelled AVX512 on consumer big-little CPUs. AMD's version of efficient c-cores will be far more capable in MT workloads than little cores

Which two generations? Nonsense. The first SKU with c-cores will be Bergamo with 128 c cores, to be released this summer. The CPU is already in test systems of hyperscalers. It's the first ever product with 16-core chiplets, each with 8 core CCX.

Most advanced and complex technologies usually come to server space that needs it, and later trickle down consumer segment.

Hi Tek-Check, tech-checking time!

xkAXyifpYm1fs5Hv.jpg


Without context or just briefly observing the above, the less informed notion being 600-series "consumer level" boards will now be officially supported until 2026, beyond the initial 2025 plan. The immediate thrill being maybe another 2 Generations support beyond 8000. Digging deeper, its a page pulled from a server deployment plan of action and to make matters worse the road-mapped parts displayed from 2022-2024 are APUs (assuming the "+" signifies "integrated" only)

So what on earth are we looking at here? I've lost my marbles with this sort of mind-trucking disorientation and hope someone can shed some light and help me find them (the marbles that is)
 
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I've heard that Zen4c is pretty much Zen4 with less cache. I've always pictured that it's Zen4 but with the layout more computer-generated, so it's more area-efficient but can't clock as high. With these differences, I think a Zen4c core would perform very similar to a Zen4 core that's been clocked down because many cores are loaded and they can't all boost. So in an AMD CPU with a Zen4 chiplet and a Zen4c chiplet, if all cores are loaded, scheduling a new independent thread on a Zen4c core probably wouldn't result in much less performance than a Zen4 core. So as long as the scheduler prioritizes the Zen4 cores until most of them are busy, I imagine there won't be any situations that see a significant loss in performance.
It's still something for the scheduler to sort out, so I don't trust it.
 
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if amd were to release a 7950xtx that is on par with 4090, nvidia will release the 4090ti with eye watering prices...
 
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So what on earth are we looking at here? I've lost my marbles with this sort of mind-trucking disorientation and hope someone can shed some light and help me find them (the marbles that is)
What exactly would you like to know?
2024 desktop - Zen5 with RDNA3.5 (enhanced, refresh) graphics. This is Granite Ridge vanilla and X3D SKUs
~2024 mobility at CES - Zen4 with RDNA3+ (enhanced, refresh) graphics. This is Strix family, and Hawk Point refresh
~2025 mobility at CES - Zen5 with RDNA3.5 graphics - Fire Range HX
~2025 mobility at CES - Zen5 with RDNA4 graphics - Strix family Halo, possibly 'mega-APU'
 
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if amd were to release a 7950xtx that is on par with 4090, nvidia will release the 4090ti with eye watering prices...
It is of questionable relevance imho. Far more important is that they release strong midrange right now. They can exceed a 4080, that's more than fine. We all know a 7950XTX is just going to draw a massive amount of power to get faster.
 
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It is of questionable relevance imho. Far more important is that they release strong midrange right now. They can exceed a 4080, that's more than fine.
Nvidia likes to keep the performance crown title though
 
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Nvidia likes to keep the performance crown title though
Yeah so why escalate beyond your own comfort zone. AMD has tried this before, it wasn't great. I'd rather see them go fast on gaining better efficiency out of their chiplet tech. Refinements.
 
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Yeah so why escalate beyond your own comfort zone. AMD has tried this before, it wasn't great. I'd rather see them go fast on gaining better efficiency out of their chiplet tech. Refinements.
oh for sure i want the power requirements of those gpu and heat output to drop but i dont think it will happen at the highest end of the product stack maybe in the mid high end
 
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Nvidia likes to keep the performance crown title though
Dude, the article is about CPUs with integrated graphics, and not about discrete GPUs. Focus.

Nvidia is not a topic here. The only thing you can say is as graphics on Zen5 APUs get better, Nvidia will cancel more mobile GPUs and there will be more space in laptops for storage and great power efficiency without discrete GPUs That's all to it.
 
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It's mentioned in the context of processor integrated graphics. This is what AMD told us last year already. Nothing new.
Not exactly. Have a quick re-read of the second paragraph. In fact, iGPUs aren't even mentioned at all.
 
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I bet this is so the 8000 CPUs can go with the 8000 GPUs.

OR: Since Zen 4 is identical to Zen 3 except for DDR5 support and the shrink (which enables the higher clocks), maybe they're holding back a digit because this should be Zen 4 because the 7000 series was really a half-measure upgrade (when you compare to each prior Zen - Zen to Zen 2? Major architectural changes. Zen 2 to Zen 3? Almost as major. Zen 3 to Zen 4? AMD configured the IMC for DDR5, maybe tweaking it slightly. I don't know if it's them who optimizes their design for the new process (transistor spacing/doubling etc.), or the company they contract, but if it's not them, AMD literally did nothing for Zen 4.

AMD: Don't do what Intel did and reuse the same architecture with minor IMC and process improvements for 5 (FIVE) generations (6th, 7th, 8th, 9th, 10th).
 
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AMD literally did nothing for Zen 4.
Zen 4 wasn't as big a change as Zen 3 or Zen 2, but it still increased IPC far more than any of Intel's lost generations did. Adding AVX-512, redesigning for higher clock speeds, and moving to a new process was a motivator for reducing risk, and they reduced risk by modifying the Zen 3 core. Chips and Cheese has a good summary of this in their Zen 4 deep dive series. This table is reproduced from there, and compares the major changes in Zen 4 to the changes in Zen 2.

AreaZen 4 over Zen 3Zen 2 over Zen 1(+)Comment
Branch PredictorLarge but unspecified improvements
L1 BTB size increased by 50%, L2 BTB gets moderate capacity increase
TAGE predictor implemented for L2
L0, L1 BTB size doubled. L2 BTB gets 75% capacity increase
Higher density probably allows for larger BTB structures
Op Cache~68% op cache capacity increaseCapacity doubled from Zen 1, but L1i capacity halvedHigher density makes a op cache capacity increase feasible
Reordering CapacityVector registers extended to 512-bits to handle AVX-512Vector registers extended to 256 bitsHigher density makes a large increase in register file capacity is acceptable
Scheduling and ExecutionNo scheduling capacity change
No execution pipe layout changes
Integer scheduling queues get 16 entries, up from 14
AGU scheduler unified
Extra AGU pipe added
Reduce risk by avoiding major scheduling layout changes
Vector ExecutionNo significant change to most commonly used execution units128-bit FP and vector units get width doubled to 256 bits
L1D BandwidthNo significant change. Still 2×256-bit load and 1×256-bit store128-bit paths doubled to 256-bits wide, giving 2×256-bit load and 1×256-bit store
L2 TLB50% capacity increase, from 2K entries to 3K33% capacity increase, from 1.5K entries to 2KTLBs are caches by another name, so again more density helps
L2Capacity doubled to 1 MB at the cost of 2 clock cycles of latencyNo change
 
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Zen 4 wasn't as big a change as Zen 3 or Zen 2, but it still increased IPC far more than any of Intel's lost generations did. Adding AVX-512, redesigning for higher clock speeds, and moving to a new process was a motivator for reducing risk, and they reduced risk by modifying the Zen 3 core. Chips and Cheese has a good summary of this in their Zen 4 deep dive series. This table is reproduced from there, and compares the major changes in Zen 4 to the changes in Zen 2.

AreaZen 4 over Zen 3Zen 2 over Zen 1(+)Comment
Branch PredictorLarge but unspecified improvements
L1 BTB size increased by 50%, L2 BTB gets moderate capacity increase
TAGE predictor implemented for L2
L0, L1 BTB size doubled. L2 BTB gets 75% capacity increase
Higher density probably allows for larger BTB structures
Op Cache~68% op cache capacity increaseCapacity doubled from Zen 1, but L1i capacity halvedHigher density makes a op cache capacity increase feasible
Reordering CapacityVector registers extended to 512-bits to handle AVX-512Vector registers extended to 256 bitsHigher density makes a large increase in register file capacity is acceptable
Scheduling and ExecutionNo scheduling capacity change
No execution pipe layout changes
Integer scheduling queues get 16 entries, up from 14
AGU scheduler unified
Extra AGU pipe added
Reduce risk by avoiding major scheduling layout changes
Vector ExecutionNo significant change to most commonly used execution units128-bit FP and vector units get width doubled to 256 bits
L1D BandwidthNo significant change. Still 2×256-bit load and 1×256-bit store128-bit paths doubled to 256-bits wide, giving 2×256-bit load and 1×256-bit store
L2 TLB50% capacity increase, from 2K entries to 3K33% capacity increase, from 1.5K entries to 2KTLBs are caches by another name, so again more density helps
L2Capacity doubled to 1 MB at the cost of 2 clock cycles of latencyNo change
Reused or not, it is way faster. That's what counts, imo.
 
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I'm genuinely surprised. Could've sworn the 8000s would come as a rebrand of the 7000s in 4nm or something. And that Zen 5 would come later. This is very early.
 
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Sure but AMD is sitting on this "c" type core technology since 2 gens now and is not doing anything on the client segment with it. Intel is about to bring 8+32 cores to the market and AMD will remain with just 16 big cores which won't win either the single or the multi threaded benches. It will just be more energy efficient. I would like to see a 8 + 16 from AMD at some point.
The only reason AMD needs to do something about it, is marketing reasons. And if they do something about it, again, it will be marketing reasons. Intel is going to keep offering 8 P cores as long as it is not getting humiliated in the benchmarks. When 8 P cores start looking bad in some benchmarks, only then Intel will go up to 10, 12 or 16 P cores. 16 Zen cores are more than a match for any Intel model on the market. But yeah, "32 cores", "40 cores", do sound like much more than "16 cores". Even when benchmarks say otherwise.
 
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