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AMD Dragged to Court over Core Count on "Bulldozer"

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So that means that what the OS reporting is wrong? It clearly says Cores: 4, Logical processors: 8

If you right-click on the graph, left click and highlight "graphs to show >," and select Logical Processors, it might show 16 little graphs of "FordGT90Concept please insert what you want to call it in here because you feel strongly that AMD must burn in a fire for their fraudulent misrepresentation of cores" to further prove your point, Vulkan. If it doesn't show 16 little graphs, then on an ironic side, it would support Ford's point. Maybe? Doubt it.

Now that I think about it, looking at your performance tab, Vulkan, maybe AMD just markets it's CPUs as having X amount of Logical Processors, but they call it "Core Processors. Intel market CPUs based on y-amount of Cores which are really 2 Logical Processors to 1 Core. I think that's one part of where the problem occurs between FordGT90Concept and others having their disagreements.

If we go back to the original Topic of Discussion, the Lawsuit is probably dead on arrival. I don't believe the court is going to award damages. At best, it's a marketing blunder on AMD's end.
 

FordGT90Concept

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It'll show 8. Logical Processors graphs always matches Logical Processors text.


...maybe AMD just markets it's CPUs as having X amount of Logical Processors...
And that's the problem. Only AMD does that and only for the Bulldozer/Piledriver/Steamroller series of processors; hence, sued.
 
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Negative. Cores are complete compute units. It would be classified as a single core with 4 threads per core by anyone that isn't AMD.

@Pill Monster: Since you clearly don't like scholarly articles, try Wikipedia on for size: https://en.wikipedia.org/wiki/Simultaneous_multithreading
All of the above explain SMT in detail. Some describe Hyper-Threading in detail.
I love scholarly articles.

What I don't like is the strawman approach of referencing materialto validate a point without specifying the actual content which supposedly validates the point
The strawman doesn't know if there is any supported evidence in the article, but he's hoping there is and other guy will find it and be disproven.


I don't have time for this shit.
 
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It'll show 8. Logical Processors graphs always matches Logical Processors text.



And that's the problem. Only AMD does that and only for the Bulldozer/Piledriver/Steamroller series of processors; hence, sued.

So if you guys will,....help me to understand why this PC has eight Cores (little green boxes) that all go to work when I run the CPU-Z multi-thread Benchmark? Is it eight,....or just a tricky four?

AMD FX-9590

Boogar.JPG
 
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2mins on Google and look what I found - Intel whitepapers with a crystal clear explanation of HT, just for you.

"A single processor appear as 2 logical processors". APPEAR. How does SMT work when there is only one physical core? Because it's using software, obviously.

See where it says OS can SCHEDULE a thread. Note SCHEDULE. Not excecute. SCHEDULE.

If u don't get that then u never will.
 
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2mins on Google and look what I found - Intel whitepapers with a crystal clear explanation of HT, just for you.

"A single processor appear as 2 logical processors". APPEAR. How does SMT work when there is only one physical core? Because it's using software, obviously.

See where it says OS can SCHEDULE a thread. Note SCHEDULE. Not excecute. SCHEDULE.

If u don't get that then u never will.

within the same document, 4 pages later, you can easily reach it by searching "5%" as keyword
intel said:
This implementation of Hyper-Threading Technology added less than 5% to the relative chip size and maximum power requirements, but can provide performance benefits much greater than that.
it doesn't explicitly say additional transistors but most likely there're some extra stuff within the chip compared with implementation without HT.
I don't think the addition hardware (if any) is for computing though. Can't be an additional core at all.
 

FordGT90Concept

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So if you guys will,....help me to understand why this PC has eight Cores (little green boxes) that all go to work when I run the CPU-Z multi-thread Benchmark? Is it eight,....or just a tricky four?

AMD FX-9590

View attachment 69065
Because FX-9590 has 8 logical processors and 4 cores (two-threads per core). Windows 8 and newer shows the break down (sockets, cores, and logical processors) in Task Manager where Windows 7 and older do not.

"A single processor appear as 2 logical processors".
That's the nature of SMT. It tells the OS to send it more threads. I've seen 2- (e.g. Pentium 4 w/ HT through Core i7-6700K), 4- (e.g. UltraSPARC T1), and 8-way (e.g. SPARC T5) SMT implementations.

How does SMT work when there is only one physical core?
The scheduler in each core shuffles between the two threads filling in gaps in core resources better utilizing the hardware resources in the core. As the name implies, the threads execute simultaneously like a dual core would but it lacks the hardware resources to get dual-core-like performance. SMT (all versions) is designed to improve throughput.

Bulldozer is unique in that they put more hardware resources in it to improve SMT performance which is a good thing; AMD's mistake was calling it an "8-core" when it clearly is not.

Because it's using software, obviously.
There is zero software involved beyond the usual when dealing with a multiprocessor.

See where it says OS can SCHEDULE a thread. Note SCHEDULE. Not excecute. SCHEDULE.
All threads need to be scheduled before they can execute. For HTT to be of any use, a thread has to be scheduled for two logical processors of the same core at the same time.

within the same document, 4 pages later, you can easily reach it by searching "5%" as keyword

it doesn't explicitly say additional transistors but most likely there're some extra stuff within the chip compared with implementation without HT.
I don't think the addition hardware (if any) is for computing though. Can't be an additional core at all.
Yeah, Hyperthreading performance, depending on task, can be something like -2.5% to 30%. 5% average sounds fair.

It does take some extra transistors (I don't think Intel ever said how many) to add SMT to a core but the goal is to utilize far more transistors that would otherwise not be used down the pipeline.
 
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The Bulldozer family groups pairs of cores into modules. Within these modules, some of the hardware is shared between the two cores. Performance problems can occur when both cores try to use this shared hardware heavily at the same time. This is similar, if less pronounced, to the per-thread performance penalty of running two threads on the same physical core using Intel's Hyperthreading.

In the early members of the family (Bulldozer and Piledriver), the instruction decoder (capable of decoding four instructions per cycle) is shared. It decodes instructions for one core each cycle, switching to the other core (if it's active) on the next cycle. In later members of the family (Steamroller and Excavator), a separate decoder is provided for each core, eliminating this bottleneck.

In all members of the family, the L1 I-cache and D-cache are shared. Since these caches are quite small (compared to Phenom II), this causes cache thrashing at a higher level when both cores are active than when only one is. The L1 caches are larger in Excavator than in previous members of the family, which contributes to its better efficiency.

The FPU is also shared in all members of the family. Most FPU instructions are multiplies or adds, so they use the FMAC pipelines, of which there are two per module. When both cores are running FPU-heavy code, effectively only one FMAC pipeline is available to each core. This is however no worse than in Phenom II, which had one multiplier and one adder in its FPU, in separate pipelines.




This is a diagram for one module, which has 2 cores. It has 2 integer units, 1 FPU, and shares an L2 cache. Conceptually, it is twice as fast at integer math in a thread, and half as fast in floating point math.

Since most server/rendering workloads are integer based, CMT scales well in multi-threading - AS LONG AS the threads are being run correctly on modules, and not split between multiple modules unnecessarily.

Windows 7 has an issue with how Bulldozer-based processors get processor threads scheduled. W7 treats them like fully independent cores, and will willy-nilly schedule threads wherever. This can cause tasks that otherwise should share FPU resources, to split across multiple modules and will cause performance degradation.

This was changed in Windows 8/8.1/10, by treating the processor as a 4 core, 8 thread chip (instead of 8 core, 8 thread) in order to properly schedule threads. On a high level, this actually emulates SMT (Hyperthreading) and results in a decent performance boost in W8/W10 for AMD processors.

There is a patch (manual install) for windows 7 that makes it schedule in the same manner, though doesn't change the appearance of task manager. You still see all 8 cores.

I don't know who pissed in your tea Ford. You also keep stating your opinion as fact.
 
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Because FX-9590 has 8 logical processors and 4 cores (two-threads per core). Windows 8 and newer shows the break down (sockets, cores, and logical processors) in Task Manager where Windows 7 and older do not.


That's the nature of SMT. It tells the OS to send it more threads. I've seen 2- (e.g. Pentium 4 w/ HT through Core i7-6700K), 4- (e.g. UltraSPARC T1), and 8-way (e.g. SPARC T5) SMT implementations.


The scheduler in each core shuffles between the two threads filling in gaps in core resources better utilizing the hardware resources in the core. As the name implies, the threads execute simultaneously like a dual core would but it lacks the hardware resources to get dual-core-like performance. SMT (all versions) is designed to improve throughput.

Bulldozer is unique in that they put more hardware resources in it to improve SMT performance which is a good thing; AMD's mistake was calling it an "8-core" when it clearly is not.


There is zero software involved beyond the usual when dealing with a multiprocessor.


All threads need to be scheduled before they can execute. For HTT to be of any use, a thread has to be scheduled for two logical processors of the same core at the same time.


Yeah, Hyperthreading performance, depending on task, can be something like -2.5% to 30%. 5% average sounds fair.

It does take some extra transistors (I don't think Intel ever said how many) to add SMT to a core but the goal is to utilize far more transistors that would otherwise not be used down the pipeline.

in the document, intel claimed 5% additional die size. I personally interpret this as ~5% additional transistors.
The 5% figure here isn't for performance but I agree you claim for -2.5% ~ 30% performance increment though.
 

FordGT90Concept

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This was changed in Windows 8/8.1/10, by treating the processor as a 4 core, 8 thread chip (instead of 8 core, 8 thread) in order to properly schedule threads. On a high level, this actually emulates SMT (Hyperthreading) and results in a decent performance boost in W8/W10 for AMD processors.
Got a source for that? I get that Bulldozer has a different logical processor order (0, 1, 2, 3, 4, 5, 6, 7) compared to HTT (0, 1, 2, 3, 4, 5, 6, 7) but the underlined part doesn't make sense.

By the way, the fact the order matters is proof they aren't cores. Legitimate cores have no preference; operating systems can park and unpark them as much as it wants as well as schedule whatever it wants wherever it wants.

I don't know who pissed in your tea Ford.
I don't drink tea. :laugh:

in the document, intel claimed 5% additional die size. I personally interpret this as ~5% additional transistors.
The 5% figure here isn't for performance but I agree you claim for -2.5% ~ 30% performance increment though.
My bad; thanks for the clarification.
 
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within the same document, 4 pages later, you can easily reach it by searching "5%" as keyword

it doesn't explicitly say additional transistors but most likely there're some extra stuff within the chip compared with implementation without HT.
I don't think the addition hardware (if any) is for computing though. Can't be an additional core at all.
by software I meant Windows, assigming threads to non existent cores lol OS is oblivious to what's going on...as usual it belives what the BIOS says.


And yeah from the whitepaper OOE (out of order execuction) has to do with it, and some extra transistors....
They even say (on page 8 I think) the primary differnce between HT and True is true cores never switch between threads, the HT cores halt the execution and switch threads constantly.


And of course all resources are shared, lol







Nothing to see here .....nothing new at least.
 
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by software I meant Windows, assigming threads to non existent cores lol OS is oblivious to what's going on...as usual it belives what the BIOS says.


And yeah from the whitepaper OOE (out of order execuction) has to do with it, and some extra transistors....
They even say (on page 8 I think) the primary differnce between HT and True is true cores never switch between threads, the HT cores halt the execution and switch threads constantly.


And of course all resources are shared, lol







Nothing to see here .....nothing new at least.

I'm not saying HT has extra compute resource that's not being shared. I just disagree your claim that HT is a purely software implementation. Intel did claim there'e a 5% die size increment and I personally interpret this as ~5% additional transistors.
 
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I'm not saying HT has extra compute resource that's not being shared. I just disagree your claim that HT is a purely software implementation. Intel did claim there'e a 5% die size increment and I personally interpret this as ~5% additional transistors.
I didn't "claim" HT was purely software so don't mince my words. I said as far as SMT goes cores it's software which it is.

The cores don't exist except in Windows Task Manager. The kernel schedular assigns threads to cores which in turn get scheduled, not executed...

You're detracting from the main debate anyway which is SMT. SMT is not here, as Intel said, - it's a concept.


Nothing else to say really,.
 

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The part you circled is where Bulldozer is unique. There's a large chunk of silicon that isn't shared. That's also why it is not technically SMT--at least not entirely (I like to call it "hybridized"). But that's not what the lawsuit is about; the lawsuit is about AMD advertising "8-core" when the definition of "core" has to be stretched beyond the breaking point in order to describe a Bulldozer "integer core."

I said as far as SMT goes cores it's software which it is.
HTT isn't software--no SMT implementation is.

The cores don't exist except in Windows Task Manager.
If SMT is enabled, they appear everywhere from BIOS to operating system.
 
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I didn't "claim" HT was purely software so don't mince my words. I said as far as SMT goes cores it's software which it is.

The cores don't exist except in Windows Task Manager. The kernel schedular assigns threads to cores which in turn get scheduled, not executed...

You're detracting from the main debate anyway which is SMT. SMT is not here, as Intel said, - it's a concept.


Nothing else to say really,.

yes the extra core doesn't exist. However the extra thread isn't a software implementation. It's not some pieces of code within BIOS makes OS recognize the extra thread. The extra hardware within CPU Die does the job.
In fact, the HT of Xeon Phi (which is a rare case) can't be disabled. By all means the extra thread is a hardware implementation other than software implementation.
 
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Quick note before vacating this thread , I just remembered the reason SMT even came up was to illustrate how BD does have 8 real cores.

In that Intyel doc it states Xenon whitepaper HT threads canot SMT iover it's there in tyhe article plain it staesXenon has a limit of 6 threads
yes the extra core doesn't exist. However the extra thread isn't a software implementation. It's not some pieces of code within BIOS makes OS recognize the extra thread. The extra hardware within CPU Die does the job.
In fact, the HT of Xeon Phi (which is a rare case) can't be disabled. By all means the extra thread is a hardware implementation other than software implementation.

I'm not stupid mate, troll harder.... you sound ridiculous.







Anyway back to why SMT came up to begin with. It's to illustrate to u Ford if u even care, why BD does have 8 real cores.


In that intel whitepaper it says a 12 core Xenon with HT is capable of sending up to 6 commands per clock cycle,. Naturally because it has only 6 cores to execute them on. SMT on 6 cores, not 12. = 6 real cores.


An 8 core Vishera send 8 commands per clock cycle because it executes 8 threads on 8 cores. That's 8 threads similtanesly= SMT = real cores.




Time to vacate the thread ......
 

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An 8 core Vishera send 8 commands per clock cycle because it executes 8 threads on 8 cores. That's 8 threads similtanesly= SMT = real cores.
I get you're pissed off at people seeing this differently to yourself, but I don't think it's as clear cut as that and maybe you'll respond to my post.

Why? Take the case of a Bulldozer CPU with just one module enabled. Execute a thread on one integer unit and it gives a certain performance. Now execute a second thread on the other core and the performance of each thread is less than one thread on one core and there's no way that this performance hit can be alleviated by better support hardware either. It's even worse with the FPU as there's only one of them, giving truly crap performance. This only happens because of the siamesed nature of the cores. It doesn't happen on AMD's older multicore CPUs nor on Intel's, potential memory bus bottlenecks aside.

Note that a similar performance hit happens on Intel too when HT is engaged and you don't see Intel calling that second virtual core a full CPU like AMD does. I remember seeing this graphically illustrated when I used to run the SETI@Home project on my single core Pentium 4 with HT more than a decade ago, before they went BOINC. Running two threads would case each individual thread to have something like 75-85% of the performance of just one, but overall performance was higher as two were being worked on at once.

Oh yeah, AMD pulled a number on us all right by making such a hybrid processor and confusing the definition of what a core is. :rolleyes: I remember the real "wtf?!" feeling I had when I first looked at that Bulldozer architecture diagram and it turns out I was right from its lack of performance. AMD tried to save a few pennies with this strategy and it bit them in the ass with poor performance, poor sales and now a lawsuit. Someone over there was very stupid.
 
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I get you're pissed off at people seeing this differently to yourself, but I don't think it's as clear cut as that and maybe you'll respond to my post.

Why? Take the case of a Bulldozer CPU with just one module enabled. Execute a thread on one integer unit and it gives a certain performance. Now execute a second thread on the other core and the performance of each thread is less than one thread on one core and there's no way that this performance hit can be alleviated by better support hardware either. It's even worse with the FPU as there's only one of them, giving truly crap performance. This only happens because of the siamesed nature of the cores. It doesn't happen on AMD's older multicore CPUs nor on Intel's, potential memory bus bottlenecks aside.

Note that a similar performance hit happens on Intel too when HT is engaged and you don't see Intel calling that second virtual core a full CPU like AMD does. I remember seeing this graphically illustrated when I used to run the SETI@Home project on my single core Pentium 4 with HT more than a decade ago, before they went BOINC. Running two threads would case each individual thread to have something like 75-85% of the performance of just one, but overall performance was higher as two were being worked on at once.

Oh yeah, AMD pulled a number on us all right by making such a hybrid processor and confusing the definition of what a core is. :rolleyes: I remember the real "wtf?!" feeling I had when I first looked at that Bulldozer architecture diagram and it turns out I was right from its lack of performance. AMD tried to save a few pennies with this strategy and it bit them in the ass with poor performance, poor sales and now a lawsuit. Someone over there was very stupid.


Oh please...just go away will you. I see things differently? You mean me and 95% of the other people who posted in in this abortion of a thread. Theres nothing to talk about, BD/PD has 8 cores, and the frivilous lawsuit will die




The topic was discussed at length when the chip got released. Seems like a bad case of dejavu..... sorry if I don't feel like revisiting the past....
 
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Well the guy can sue all he wants. If they said that the FX 8xxx has 8 cores and a software reads it as 8 cores it's not false advertising. The fact that an intel quad core can beat it is not relevant in this case.

I don't think he will win in court. Either way I'm happy with my choice. I didn't have money for anything better at the time.
 

qubit

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Oh please...just go away will you. I see things differently? You mean me and 95% of the other people who posted in in this abortion of a thread. Theres nothing to talk about, BD/PD has 8 cores, and the frivilous lawsuit will die




The topic was discussed at length when the chip got released. Seems like a bad case of dejavu..... sorry if I don't feel like revisiting the past....
No, it has 4 siamesed cores who's performance suffers when running two threads on one. I tried to sympathize with you, but you got one hell of a shit attitude. I gave you a reasonable explanation of how I see it, so all you had to do is discuss it in a reasonable manner with me and show some respect. I'm not going anywhere.

Yeah, go on, just get off this thread like you were gonna. :nutkick:
 
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the54thvoid

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Someone close this tired useless roundabout thread. We'll find out in about 'god knows how many' years which way it goes.

Until then it's just an utterly futile piss take of a discussion with two distinct camps, smashing their heads against walls.

You say potato, I say potato core.
 

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