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AMD Ryzen 9000 Zen 5 Single Thread Performance at 5.80 GHz Found 19% Over Zen 4

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So he thinks AMD was looking at CPU-Z, or anyone was? That's absurd.

He doesn't "think", they were testing it. AMD literally had CPU-z in the official IPC slide in case you want to have a look, and his quote was immediately after the slide.

1717101321246.png


Note CPU-z on the far left with no change.

That might be because, Zen 3 and Zen 4, are not much different at the core level. They mostly changed the IO / memory / cache.

And yet the quote itself is this: "Zen 4 received improvements like a larger micro-op cache, better branch prediction, and doubled L2 cache capacity. Those would help a lot of applications, but not CPU-Z. Thus, CPU-Z’s benchmark ends up being useless to both CPU designers and end users"

So yes, there were core changes. And those improvements certainly contributed to the 13% IPC gain and yet no gain in the CPU-z benchmark, because the a beefier front end doesn't affect the result. So let me understand this correctly, is a larger micro op-cache, which affects a lot of real world workloads, part of your 'pure IPC' calculation? Or like..better branch prediction? How about having larger L2 caches, which will certainly affect a lot of workloads but not CPU-z? Or is your definition of a pure IPC benchmark one that only really tests the backend of a CPU and fits into L1 cache?

Of course it does. If it does not fit in L1, what exactly are you testing?

L1<->L2 latency and bandwidth? L2<->L3 Latency and bandwidth? L3<-> main memory latency and bandwidth? Yes on all counts.

I'm sorry, but just fitting into L1 cache doesn't make it a great, or a 'pure IPC' test. A higher L1 or L1>L2 bandwidth will contribute to, but not automatically make it a 'pure IPC' test . To put it simply, a larger L2 cache in a cache starved design will net huge IPC gains in most applications but an absolute zero gain in CPU-z single core bench. Same with a much larger micro-op cache. So essentially the CPU-z test is mostly testing the backend of a CPU, and hits the FP register particularly hard.

Work on that reading comprehension thing. It does test branch predictors, just not to the degree that "chipsandcheese" wants.

I'm going to ignore that unnecessary insult of sorts and get to it. Improved branch predictors make next to no difference in the CPU-z benchmark and certainly no difference in the single core bench. To quote, this is how basic their test of the branch prediction is: "Even Goldmont Plus has no problem tracking CPU-Z’s branches". Hell, even Bulldozer has very little problems with that terrible branch predictor and that's saying something. It's not what "chipsandcheese" wants, it's what they are seeing in the results. My reading comprehension was fine, I just didn't wanna add a ton of explanation thinking you also understand that branch predictors make next to no difference in that bench. Well now you know.

You seem to have the idea that this CPU-z test which fits into the L1 cache is a pure IPC test. A chips and cheese article refutes that. The test not really testing a CPU's frontend refutes that, as real world benches benefit a lot from it. Branch predictors not affecting the single core result refutes that. A larger micro-op cache not affecting the result refutes that. I can go on, but i'll stop here. If you still think this CPU-z bench is a pure IPC bench so be it. It would simply mean your definition of IPC is different from mine. For me, IPC gains are calculated using an average of test results which individually test different parts of the CPU or a more rounded single bench that is atleast affected by changes in front end, execution and backend. A singular test that doesn't change from an increase in micro-op cache, larger L2 and generally beefier front end doesn't really fit the definition of a 'pure IPC' bench.

I'm going to stop arguing with you over this and leave with a quote from them:
"What limits computer performance today is predictability, and the two big ones are instruction/branch predictability, and data locality - Jim Keller, during an Interview with Dr. Ian Cutress.
That’s not just Jim Keller’s opinion. I’ve watched CPU performance counters across my day-to-day workloads. Across code compilation, image editing, video encoding, and gaming, I can’t think of anything that fits within the L1 cache and barely challenges the branch predictor. CPU-Z’s benchmark is an exception. The factors that limit performance in CPU-Z are very different from those in typical real-life workloads."
 
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ARF

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Unfortunately this is fake and the original source removed it

Makes sense to be either under very high overclock, or to be fake altogether.
As mentioned above, the IPC increase from Zen 3 to Zen 4 was a miserable 1%, and CPU-Z obviously doesn't recognise (or is "optimised" to be running slow on) the AMD Ryzen CPUs properly, so we can't really expect over 18% IPC increase, unless the bench is changed. I don't know how the newer 19.01.64 AVX2 (beta) and 19.01.64 (beta) compare to the default 17.01.64 test.
 

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What's your power draw to achieve 980 score? 500 watts from the CPU alone?
Goes up to 250W on multi threaded work and about 40-50W on a single thread. I don't think I've written somewhere that top OCed Intel chips like 14900K(S) are more power efficient because they are not. But at least with Intel chips you can decide if you want to throw the efficiency out the window and do a max score or you want to sacrifice some performance for efficiency. If I wanted my 14900K to score 900 points in CPU-Z then I could lower the vcore quite a bit resulting in far greater efficiency probably close to what AMD has.
Anyway the point is that 900 1T cpu-z score for next gen AMD is bad since it hardly matches Intels curren't gen. And let's not even mention Apple M4 which blows them all out of the water.
 
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Now that's an enticing bump if true. Time for the leaks...
19% more performance or 19% IPC ? 19% performance would be a bit disappointing knowing that ZEN 5 is supposed to be a new architecture... On 1 core it's not bad, even though 30% would be much better imho.
 

ARF

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19% more performance or 19% IPC ? 19% performance would be a bit disappointing knowing that ZEN 5 is supposed to be a new architecture... On 1 core it's not bad, even though 30% would be much better imho.

Of course. If those low numbers confirm, then it will be another generation which will be skipped by the majority of users with ease, and AMD will have to decrease the pricings, which will negatively reflect its financial sheets.
Extremely conservative generation...
 
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19% more performance or 19% IPC ? 19% performance would be a bit disappointing knowing that ZEN 5 is supposed to be a new architecture... On 1 core it's not bad, even though 30% would be much better imho.

Well, then visit AMD with *your* CPU design that improves upon Zen4 by 30% on average. They won't reject you and will want to take a look at the design.
 
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Well, then visit AMD with *your* CPU design that improves upon Zen4 by 30% on average. They won't reject you and will want to take a look at the design.
Haha yeah but that's their job you see...they hired Jim Keller for that several years ago!
I'll be buying a ZEN 5 3D (for Gaming) so I hope they improved the latency with the interconnect bandwidth. 19% more performance for a new architecture is not bad at all, but it's not crazy good either! ZEN 5 was hyped as the Messiah of CPUs so yeah. Maybe ZEN 6 will be the true "Game Changer"
 
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ZEN 5 was hyped as the Messiah of CPUs so yeah.

I have been following Zen5 leaks from time to time, and I don't think that it was presented as a "Messiah CPU".

All Zen CPUs (that is: Zen 1, Zen 2, Zen 3, Zen 4) had 6-wide dispatch since the beginning, while at the same time the IPC difference between Zen1 and Zen4 is fairly large, thus if by "Repipelined frontend" AMD in their own Zen5 slide meant changes in the frontend to supply the 8-wide dispatch in Zen5 with enough µops per clock cycle, then the claim about "Repipelined frontend" would be quite accurate and would reflect reality. Whether the term "New grounds up microarchitecture" used in AMD's slide was an overly bold statement or wasn't is to be seen about 1 week from today - so we wait.

Well, of course AMD is *today* busy finishing the Zen6 design (in parallel to launching Zen5) and already knows the approximate/projected/simulated IPC of the future Zen6 CPU. But we need to wait - so we wait. Of course we are encouraging them to their best and push some limits!

From https://git.kernel.org/pub/scm/linu.../?id=29c73fc794c83505066ee6db893b2a83ac5fac63 (file pipeline.json):

Code:
"Total dispatch slots (up to 8 instructions can be dispatched in each cycle)."
 
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I really want ZEN 5 to be a great architecture and succeed but it's been talked so much for years that it doesn't sound that much impressive anymore lol. I guess leakers or people making fake news just spoil it for us because we have high expectations and then end up being somewhat disappointed.
I have been following Zen5 leaks from time to time, and I don't think that it was presented as a "Messiah CPU".

All Zen CPUs (that is: Zen 1, Zen 2, Zen 3, Zen 4) had 6-wide dispatch since the beginning, while at the same time the IPC difference between Zen1 and Zen4 is fairly large, thus if by "Repipelined frontend" AMD in their own Zen5 slide meant changes in the frontend to supply the 8-wide dispatch in Zen5 with enough µops per clock cycle, then the claim about "Repipelined frontend" would be quite accurate and would reflect reality. Whether the term "New grounds up microarchitecture" used in AMD's slide was an overly bold statement or wasn't is to be seen about 1 week from today - so we wait.

Well, of course AMD is *today* busy finishing the Zen6 design (in parallel to launching Zen5) and already knows the approximate/projected/simulated IPC of the future Zen6 CPU. But we need to wait - so we wait. Of course we are encouraging them to their best and push some limits!

From https://git.kernel.org/pub/scm/linu.../?id=29c73fc794c83505066ee6db893b2a83ac5fac63 (file pipeline.json):

Code:
"Total dispatch slots (up to 8 instructions can be dispatched in each cycle)."
 
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I really want ZEN 5 to be a great architecture and succeed but it's been talked so much for years that it doesn't sound that much impressive anymore lol. I guess leakers or people making fake news just spoil it for us because we have high expectations and then end up being somewhat disappointed.
 
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I have been following Zen5 leaks from time to time, and I don't think that it was presented as a "Messiah CPU".

All Zen CPUs (that is: Zen 1, Zen 2, Zen 3, Zen 4) had 6-wide dispatch since the beginning, while at the same time the IPC difference between Zen1 and Zen4 is fairly large, thus if by "Repipelined frontend" AMD in their own Zen5 slide meant changes in the frontend to supply the 8-wide dispatch in Zen5 with enough µops per clock cycle, then the claim about "Repipelined frontend" would be quite accurate and would reflect reality. Whether the term "New grounds up microarchitecture" used in AMD's slide was an overly bold statement or wasn't is to be seen about 1 week from today - so we wait.

Well, of course AMD is *today* busy finishing the Zen6 design (in parallel to launching Zen5) and already knows the approximate/projected/simulated IPC of the future Zen6 CPU. But we need to wait - so we wait. Of course we are encouraging them to their best and push some limits!

From https://git.kernel.org/pub/scm/linu.../?id=29c73fc794c83505066ee6db893b2a83ac5fac63 (file pipeline.json):

Code:
"Total dispatch slots (up to 8 instructions can be dispatched in each cycle)."

I like your attitude. You should post more. :toast:
 
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19% more performance or 19% IPC ? 19% performance would be a bit disappointing knowing that ZEN 5 is supposed to be a new architecture... On 1 core it's not bad, even though 30% would be much better imho.
You must have loved the Intel days. IPC gains of 1-3% every two years was just amazing to behold. It will go back to this without AMD, or perhaps without Intel too!

But I will say that IMO Zen 4 and AM5 in general is very disappointing. AMD did not go nearly far enough and left themselves behind Intel until the x3D chips came out. Zen 5 really needs to address this and make the AM5 platform worth the high cost of membership. I hear Zen 5 will bring with it a refresh of AM5 with USB4 support via a MediaTek chip, which I really hope doesn't suck. Memory support on AM5 is a joke, but I hear the refresh may tackle this with an IF of 2.4GHz, officially supporting DDR5 8000, AMD desperately need this, as their memory controller on Zen 4 really is a complete joke compared to what Intel gets, even at the same speed. I also hope they also sort out the PCiE5 issues and make it more widespread than just the most expensive motherboards. But it's AMD, and they have never been particularly great with chipsets.
 
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When AMD first released the Zen2 architecture, CPU-Z's author (or Intel) decided that he didn't like the Zen2 out-performing the Intel chip at the time, so a new benchmark version was released, reducing the AMD scores (Intel scores stayed the same) by some 15%. I have never taken the CPU-Z benchmark seriously after that, as it's apparently just an Intel sponsored benchmark.


No one cares what you take seriously or not, Zen 2 was trash which was slower than Skylake, so having it beating Intel by 20% was ridiculous.
 
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No one cares what you take seriously or not, Zen 2 was trash which was slower than Skylake, so having it beating Intel by 20% was ridiculous.
LOL, My 3950x is laughing at this statement although somewhat slowly compared to todays CPU's.
 
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You must have loved the Intel days. IPC gains of 1-3% every two years was just amazing to behold. It will go back to this without AMD, or perhaps without Intel too!

But I will say that IMO Zen 4 and AM5 in general is very disappointing. AMD did not go nearly far enough and left themselves behind Intel until the x3D chips came out. Zen 5 really needs to address this and make the AM5 platform worth the high cost of membership. I hear Zen 5 will bring with it a refresh of AM5 with USB4 support via a MediaTek chip, which I really hope doesn't suck. Memory support on AM5 is a joke, but I hear the refresh may tackle this with an IF of 2.4GHz, officially supporting DDR5 8000, AMD desperately need this, as their memory controller on Zen 4 really is a complete joke compared to what Intel gets, even at the same speed. I also hope they also sort out the PCiE5 issues and make it more widespread than just the most expensive motherboards. But it's AMD, and they have never been particularly great with chipsets.

AMD leaves so much performance untapped on the IMC side it's frankly ridiculous. Even with EXPO kits there's a sizeable chunk of performance to be gained from IF overclocking and subtiming tweaks. If they can get the IF up, along with the memory controller handling higher speeds with a 1:1 ratio, they already have double digit gains right there.

On a particular workload I run, the difference in performance between EXPO 6000/2000 Mem/IF and Tuned 6000/2033 Memory/IF is 11% on the 7950x3D.
 
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AMD leaves so much performance untapped on the IMC side it's frankly ridiculous. Even with EXPO kits there's a sizeable chunk of performance to be gained from IF overclocking and subtiming tweaks. If they can get the IF up, along with the memory controller handling higher speeds with a 1:1 ratio, they already have double digit gains right there.

On a particular workload I run, the difference in performance between EXPO 6000/2000 Mem/IF and Tuned 6000/2033 Memory/IF is 11% on the 7950x3D.
Yeah, they have many weaknesses in the Zen design. Slow IF, exasperated by the terrible memory controller, undersized L2 and L3 caches, both half the size they need to be, and high latencies in general are the lowest hanging fruit. Fix all those and you're looking at a 20-30% performance improvement. But AMD are amateur, short-sighted and unfortunately now very greedy, so we have gone back to the drip, drip, drip releases, and they still can't beat Intel chips without resorting to releasing chips with the correctly sized L3 cache as a money grabbing exercise, which should have been incorporated into the Zen4 chips (and certainly Zen5) from day one. We are watching AMD slowly throw away the lead Zen 3 gave them, to a point where Intel chips are faster than AMD's non 3D cache chips.

I hear that because AMD would not use TSMC's newer 3nm class, they stuck with a slightly improved 4nm node, meaning that they have not been able to do anything more radical for Zen5. They have also kind of designed themselves into a bit of a corner regarding their chiplet design and its physical size. The AM5 socket is simply too small to be able to fit more chiplets. They needed to reduce the physical size of the chiplet before they can go and put more cores on it. They can't do anything about the IOD due to it not scaling with smaller process nodes, so only expect that to get physically larger as they are forced to add more features to it.

I hear that the new Zen5 chips, when paired with a "refreshed" AM5 motherboard will officially support DDR5 8000. But it is not clear if this is because the IF is clocked at 2.4GHz or they have simply bolted on yet another memory divider, which will only make their memory situation worse. Hopefully we will find out soon. But that leaves a bad taste in the mouth that you might need to go out and spend $300 - $500 on a "new" AM5 motherboard, just to correct something that should have been a day one feature of the AM5 platform.
 
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Not the same test but good enough for reference:
(as an offtopic sidenote - I seriously doubt the 7800X3D's 17W number)

That's quite frankly pathetic single core efficiency compared to X3D, or other forward looking COUs like Apple's M3 or Qualcom's Snapdragon. The 14000-series will be seen as a relic, as even Intel themselves are abandoning this performance at all costs approach with Lunar and Arrow Lake.
 
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That's quite frankly pathetic single core efficiency compared to X3D, or other forward looking COUs like Apple's M3 or Qualcom's Snapdragon. The 14000-series will be seen as a relic, as even Intel themselves are abandoning this performance at all costs approach with Lunar and Arrow Lake.
That's a power draw graph, not an efficiency graph.

This is the efficiency graph. Yes, the x3d looks horrible in ST efficiency, it loses in efficiency by ~50% compared to the similarly performing 13400f. I don't know how AMD achieved that amount of inefficiency, but oh boy.

 
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That's a power draw graph, not an efficiency graph.

This is the efficiency graph. Yes, the x3d looks horrible in ST efficiency, it loses in efficiency by ~50% compared to the similarly performing 13400f. I don't know how AMD achieved that amount of inefficiency, but oh boy.

Because desktop ryzens are not optimized for single threaded tasks at all in isolation, and no we're not talking about IPC here. Single threaded tasks are useless as no real world workload really uses that. Ryzens fire up the whole of their IOD for a single core, and even then it's embarrasingly...50% more efficient than the 13900K in your own graph lmao. So erm..here's the multithreaded efficiency in that very same review:

1718468973815.png


Now let's see you comment on intel's efficiency. I mean, if you have no idea how AMD acheived that level of inefficiency, what words do you have for intel? Surely worse right?
 
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Because desktop ryzens are not optimized for single threaded tasks at all in isolation, and no we're not talking about IPC here. Single threaded tasks are useless as no real world workload really uses that. Ryzens fire up the whole of their IOD for a single core, and even then it's embarrasingly...50% more efficient than the 13900K in your own graph lmao. So erm..here's the multithreaded efficiency in that very same review:

View attachment 351469

Now let's see you comment on intel's efficiency. I mean, if you have no idea how AMD acheived that level of inefficiency, what words do you have for intel? Surely worse right?
The 13900k is much faster than the 7800x 3d in ST performance so comparing their efficiency is pointless. You can see that the 13900k is slumdunking the 7950x in ST eff while being faster.

Your MT graph is useless - yes obviously the low power zen 4 parts will be at the top cause there aren't any low power Intel parts on the graph. Put all the T and non k parts in that graph and you won't find a single AMD cpu on the top 10, lol.
 
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The 13900k is much faster than the 7800x 3d in ST performance so comparing their efficiency is pointless.
I've got a migraine now - this seems like a reversal of many past discussions across many threads.
 
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The 13900k is much faster than the 7800x 3d in ST performance so comparing their efficiency is pointless. You can see that the 13900k is slumdunking the 7950x in ST eff while being faster.

Your MT graph is useless - yes obviously the low power zen 4 parts will be at the top cause there aren't any low power Intel parts on the graph. Put all the T and non k parts in that graph and you won't find a single AMD cpu on the top 10, lol.

Nah, your ST benchmark itself if useless as it has no relevance to real world workloads. Cinebench 1T and most other 1T workloads don't even make use of many of a chip's strengths, including branch predictors because there aren't that many in flight. Also as I explained to you earlier (you seemed confused by AMD's lack of efficiency in artificial ST workloads) Ryzen's, especially the dual CCD variants, have to fire up their whole IO die for 1T workloads which reduces their efficiency but they make that up and some more when it comes to MT workloads. How about you comment on the multithreaded power efficiency of 7950X3D vs 13900K, both direct competitors. AMD's power consumption and efficiency is a lot better there, would you agree?

And uh..no my MT graph isn't useless at all because there are literally like for like AMD vs Intel CPU's in there so it's an apt comparison. As you can see, Intel gets destroyed in there at every level. Your point about bringing in low power intel CPU's in the mix is funny. Why not compare directly comparable desktop CPU's like we are here? Not to mention, there are low power AMD CPU's too.

Your power consumption argument is so strange. It's like..Intel universally gets destroyed in power consumption from every reputable reviewer out there and suddenly you're like 'ohhhhh no no that's not the case look at a useless benchmark, intel uses less power here so it must be better'. Pfft


I've got a migraine now - this seems like a reversal of many past discussions across many threads.

I should've just ignored his posts, I honestly forgot for a second he's around the same level as userbenchmark and that's saying something.
 
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AMD's power consumption and efficiency is a lot better there, would you agree?
No, it just has a lower power limit.


At ISO power limits most Intel CPUs are more efficient than their AMD counterparts in MT. By a lot.
 
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