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AMD to Redesign Memory Controller in Bulldozer Chips.

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#1
This is nothing but good news :toast:

AMD to Redesign Memory Controller in Bulldozer Chips.
AMD's Future Processors Will Feature Faster Memory Controller

[09/15/2010 05:48 PM]
by Anton Shilov
-------------------------
Advanced Micro Devices continues to disclose details about its forthcoming processors with Bulldozer micro-architecture. Apparently, the company plans to redesign memory controller of its new central processing units (CPUs) in order to speed up memory access.

"There will be enhancements to our memory controllers, things we canot talk about just yet, that we expect to help reduce the time to access memory, both locally and remotely," said John Fruehe, John Fruehe, the director of product marketing for server/workstation products at AMD.

In previous-generations AMD Opteron multi-processor systems it took microprocessors two hopes to reach the information located in memory banks of other CPUs, in takes just one hope for a current generation AMD Opteron processor to reach the data in others' memory banks. One of the ways to speed up memory transfers in multi-chip systems is to implement features like HyperTransport Assist, a feature that was introduced with six-core AMD Opteron. But at present it looks like AMD's next-gen processors will not only improve memory accesses to remote memory banks, but also to local memory.

AMD's current-generation Opteron processors with eight or twelve cores have quad-channel DDR3 memory controller; next year the company's high-end server chips will "grow" to sixteen cores with the same four DDR3 memory channels and maximum memory bandwidth. Moreover, desktop chips with up to eight cores will only have dual-channel DDR3 memory controllers, which may not be enough for demanding applications.

With advances in memory controllers AMD can further improve performance of its chips and avoid memory-related bottlenecks.

http://www.xbitlabs.com/news/cpu/display/20100915174850_AMD_to_Redesign_Memory_Controller_in_Bulldozer_Chips.html
 

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#2
Hopefully they can actually pull it off, their memory controllers seem to be a real weak point with them. Going all the way back to at least 754 when they first started using an IMC, they just haven't been able to get it right.
 

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#3
The article is very vague. Who knows if they are going to successfully redesign the controllers. I sure hope so, it has been a weakness for a while.
 

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#4
LOL. I bitch about how memory control is holding back thier high-end multi-gpu vgas for a couple of weeks, and then we get an announcement saying that memory control will change?



Um, Hello, AMD, so, do you have other obvious things that you are going to change?


:rolleyes:


I mean, I know IDF is going on, but please, stop blowing hot air. If the memory controller didn't change, bulldozer might be a failure, so it HAS to change. And considering only specific scenarios really need this change, it's not really THAT important, now is it?


Well, unless AMD, wants to capture the high-end enthusiast crowd...
 
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#5
I think that article really took what John Fruehe said out of context alittle. Hes a server guy commenting on HPCs, this article made it seem like he was commenting on desktop CPUs. Read what John said here, just scroll down to the second question that Mikael Ronström asks.
 

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#6
I think that article really took what John Fruehe said out of context alittle. Hes a server guy commenting on HPCs, this article made it seem like he was commenting on desktop CPUs. Read what John said here, just scroll down to the second question that Mikael Ronström asks.
Good find, man. I think you may be very right.
 

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#7
Great to see them redesigning the memory controller for some faster access times.

Why still no move to triple channel though?, don't see anything wrong with more memory bandwidth.(though dual channel is still sufficient)

I also hope there 8 cores and mobo's are pretty cheap, may move up to Bulldozer if they are.:)
 

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#8
Why still no move to triple channel though?, don't see anything wrong with more memory bandwidth.(though dual channel is still sufficient)

Look at the differnece between Intel's triple/dual channel on i7(1156 vs 1366). It's quite obvious that AMD's memory control is a bit lacking, and it's not in the number of channels. Unganged, while not true 4-channel, splits the dual channel 128-bit controller into two 64-bit dual channel controllers. Most users are running 64-bit memorycontrol...and for some reason, it seems to be faster than 128-bit mode. They clearly need to fix 128-bit mode. Once they do, they should be on-par, if not better, than Intel's current solutions.
 
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#9
Great to see them redesigning the memory controller for some faster access times.

Why still no move to triple channel though?, don't see anything wrong with more memory bandwidth.(though dual channel is still sufficient)
I've been reading about a Quad-Channel DDR3 memory controller for Bulldozer. I mean if you look at the Bulldozer Module, it makes a lot of sense to have Quad and not Dual. Put four modules together and you have Quad-Channel. I just don't see a Dual-Channel feeding those cores.

Though is it possible to have 2 x Dual-Channel memory controllers? :confused:
 
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#11
Bulldozer will have a quad channel memory controller on its Interlagos Operton parts. As for the Zambezi octicore processor, it will still have a dual channel DDR3 only controller. However, I've been told that the Zambezi memory performance, while still only dual channel, will rival current i7 triple channel memory controllers. That is just for far away memory (RAM); L3 cache performance will also shoot up drastically.
 

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#12
Hmm, so maybe they disable "secondary controller", and this allows the speed to jump up. And there was something about 1866mhz...when 1333 is standard now...doesn't sound all that exciting.
 
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#13
Hmm, so maybe they disable "secondary controller", and this allows the speed to jump up. And there was something about 1866mhz...when 1333 is standard now...doesn't sound all that exciting.
Buy the time Bulldozer based desktop CPU's are released, we should have 1866MHz as the standard. Bulldoser is based on 1866MHz DDR3 so it makes sense.

If you look at AMD's generic slide show featuring Bulldozer they don't get into much detail about the memory controller but they do have a picture of a 8 core processor with an Integrated Memory Controller and an Integrated North Bridge Controller.
 
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#14
Orochi die shot confirms 128bit, dual channel IMC



I spy 128bit (+ 16bit ECC) mem I/O pads right there on the right edge.
I reeeeaally hoped for 3-channel 192bits just for the sake of having 6 DIMMs for a nice big soft RAMD.

you AMD!
 
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#15
Read this Quote:
the company plans to redesign memory controller of its new central processing units (CPUs) in order to speed up memory access.
It sounds like they plan on re-designing the controller now, meaning they've not done so yet? Can this be right?
 

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#16
Read this Quote:


It sounds like they plan on re-designing the controller now, meaning they've not done so yet? Can this be right?
No, it means the new CPU's will have a new memory controller. Since the new CPU's haven't been released, there's really nothing more to look into it. I think it's rather common sense that the memory controller will be redone as the current controller in PII isn't enough for those chips.
 

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#17
I think it's rather common sense that the memory controller will be redone as the current controller in PII isn't enough for those chips.

Well, you understand that few actually say so(I'm one of few that seem to realize this weakness), and most marketing tells people otherwise. Not many people understand that at default, they aren't even running 128-bit dualchannel like Intel is.

I mean, if I say AMD is running quadchannel DDR3, people jump down my throat...even tho that's basically what it is...2x64-bit dual channel.

Two duals=a quad, right? I mean, it's just like Intel's Core2 Quads...two seperate dualcore together...


I mean, OK, it's not EXACTLY quad-channel memory control, but it ain't no dualchannel like Intel's either, now is it? But AMD marketing would have you think so...


:shadedshu

Anyway, yes, it's obvious this needs to change...to us, maybe.
 
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#18
i thought AMD was dual channel not a quad because eg. 2sticks would be one channel > 2 would be the other channel < . i assumed as the later intels were triple channel means the 3rd channel could go either way.
AMD's can be ganged to 128bit but couldnt really find any real information about the performance differences accept single thread processes seem to benifit.
 
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#19
i thought AMD was dual channel not a quad because eg. 2sticks would be one channel > 2 would be the other channel < . i assumed as the later intels were triple channel means the 3rd channel could go either way.
AMD's can be ganged to 128bit but couldnt really find any real information about the performance differences accept single thread processes seem to benifit.
A board with just two slots runs dual channel, so one with 4 is quad channel.

Assuming Cadaveca is right, and I'm willing to bet a few pence he is.
 
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#20
why would amd make a song and dance about quad channel now if they already had quad channel before. also why would intel do the same about triple channel if the competition already had quad

i know that having ganged enabled (128bit) makes a big difference on everest memory read/write tests over 1000 extra point
 
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#21
thought there was already a thread on this. But word. Bulldozer def needs to bring some nice jumps in architectural improvement and live up to the codename. I personally feel bulldozer is gonna def increase memory bandwidth(always thought this before this article), and be on par with i7.

Then there's sandy bridge, which show's great overclocking for their high end chips supposedly, like 5ghz so a thread said on air. We've gotten 5ghz on air with intel's lowend stuff but the high end avg seems to be 3.8ghz-4.2ghz, so if the avg jumps on that to even 4.2ghz-4.6ghz on the high end...that's gonna be tough on AMD.
 
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#22
bulldozer needs to destroy i7 by a big margin clock for clock at stock, which i hope they do im saving now..lol
 

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#23
i thought AMD was dual channel not a quad because eg. 2sticks would be one channel > 2 would be the other channel < . i assumed as the later intels were triple channel means the 3rd channel could go either way.
AMD's can be ganged to 128bit but couldnt really find any real information about the performance differences accept single thread processes seem to benifit.
Intel's i7 triple channel is 1x128bit controller, 3x128bit channels, 2 dimms per channel.

Intel's i5/i7 dual channel is 1x128bit controller, 2x128bit channels, 2 dimms per channel.

AMD Ganged Mode is 1x 128bit controller, 2x128Bit channels, 2 dimms per channel.

AMD Unganged Mode is 2x64bit controllers, 2x128bit channels, 2 dimms per channel.

So, in unganged mode, there are two controllers, and they can both INDEPENDANTLY access the same data. Or, they can simultaneously access different data. For multi-threaded apps, this kinda works better, as ideally, you can get better bus utilization, as you have 2x the controller handling the data, which can each toss up different data to different threads. In ganged mode, one thread would have to wait while the operation for the other thread is completed(hence ganged being better for single-threaded apps only, as then the thread has exclusive control of the controller).

Memory benchmarks aren't written so truly show what is happening.
 
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#24
"Channel" of SDRAM system memory = one rank (side) of a DIMM = 64bit (8×8bit, or rarely 4×16bit).
Single channel = 64bit, dual channel = 128bit, tri channel = 192bit, quad channel = 256bit. You can't say 2×64bit dual channel is quad channel because "2×64bit" is "dual of 64bit channels", by definition.
->
Code:
Intel's i7 triple channel is 1×[B]192[/B]bit controller, [B]3×64[/B]bit channels, 3 DIMMs required, max 2 per channel.

Intel's i5/i7 dual channel is 1×128bit controller, [B]2×64[/B]bit channels, 2 DIMMs required, max 2 per channel.

AMD Ganged Mode is 1×128bit controller, [B]2×64[/B]bit channels, 2 DIMMs required, max 2 per channel.

AMD Unganged Mode is [B]2×64[/B]bit controllers, [B]2×64[/B]bit channels, 2 DIMMs required, max 2 per channel.
I mean, if I say AMD is running quadchannel DDR3, people jump down my throat...even tho that's basically what it is...2x64-bit dual channel.

Two duals=a quad, right? I mean, it's just like Intel's Core2 Quads...two seperate dualcore together...


I mean, OK, it's not EXACTLY quad-channel memory control, but it ain't no dualchannel like Intel's either, now is it?
It is dual channel and nothing more.
 
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#25
It is dual channel and nothing more.
Yeah, you are right, but having 2 controllers means it's not like Intel's dualchannel, and it's that controller difference that makes AMD slower than Intel.

I didn't think system ram memory controllers were the same bus-width as gpus...but thanks very much for the correction, as I knew something was wonky there.

The best part is, I kinda tried to look for that info...it's not easy to find...I basically guessed.


:laugh: I'm ALWAYS guessing.