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AMD to Redesign Memory Controller in Bulldozer Chips.

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#51
I don't know, can you see an enhanced Dual-Channel IMC feed 8 cores? I really think Quad-Channel is what AMD is going to use for both Desktop and server. It will keep the Bulldozer platform consistant and easy to work with.
 

JF-AMD

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#52
I can't comment on the client side, but on the server side we have absolutely no issue with the dual channel controller in Valencia keeping all 8 cores fed. I think people underestimate the capabilities of the memory controller.
 

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#53
OMG! you work for AMD!!!! i am so jealous.
 

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#54
I can't comment on the client side, but on the server side we have absolutely no issue with the dual channel controller in Valencia keeping all 8 cores fed. I think people underestimate the capabilities of the memory controller.

hmm interesting, so basically why AMD redesign it if that was not the problem ?
 

cadaveca

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#55
I can't comment on the client side, but on the server side we have absolutely no issue with the dual channel controller in Valencia keeping all 8 cores fed. I think people underestimate the capabilities of the memory controller.
Nobody is underestimating anything...because the cpu cores from server to client are so similar, and I truly seem to be running into memory controller limitations with my own rig, and have posted many benchmarks showing this.

So, currently, Phenom 2's memory controller seems in adequate. A simple increase of CPU-NB speed brings performance gains in 3D that raw clockspeed @ the core does not.

If we actually make what I consider an accurate compare between the current AMD and Intel platforms, the differences in design are quite clear, but thier implementation is not.
When it comes to high-end gaming, it seems that Intel really pulls ahead, and one of the most obvious differences is the difference in memory control.

With that said, I don't really think you can blame people for coming to that conclusion.

hmm interesting, so basically why AMD redesign it if that was not the problem ?
And this as well.


Take a gander @ X4 970 news threads...there's always someone saying "I hope the NB speed would go up too..."

People are asking for quad and duial channel for quite obvious reasons, if you ask me. It currently seems to be a large "flaw" in Phenom-based chippery.
 
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JF-AMD

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#56
hmm interesting, so basically why AMD redesign it if that was not the problem ?
Why would you build a completely new chip, from the ground up, and throw on an old memory controller.

The one in our current Opteron processors is built around a design from pre-2003 that was tweaked in 2005 and then again in 2009. Why would you keep this and not use the opportunity to completely redesign a brand new one?

Oh, and when the story said "redesign" they were not talking about redesigning a bulldozer memory controller (like we had built it and decided to change it.)
 
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#57
Good point AMD old memory controller was ok for the past but still was too slow and inefficient ever since 2008. It about time AMD completely design a brand new integrated memory controller for the new Bulldozer arch. Let me ask will be Dual-Channel or Quad-Channel? Many plan on get Bulldozer CPU with 12GB to 16GB of memory. :)
 

JF-AMD

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#58
Good point AMD old memory controller was ok for the past but still was too slow and inefficient ever since 2008. It about time AMD completely design a brand new integrated memory controller for the new Bulldozer arch. Let me ask will be Dual-Channel or Quad-Channel? Many plan on get Bulldozer CPU with 12GB to 16GB of memory. :)
Slow and inefficient? Take a look at Xeon vs. Opteron benchmarks for memory throughput.

2P Opteron ~54GB/s
2P Xeon ~37GB/s

4P Opteron ~104GB/s
4P Xeon ~75GB/s

If we are slow and inefficient I hate to think of what Intel is.
 
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#59
It is a well known fact AMDs IMC is the weakest link to there design, correct me if I am wrong. But you agree it a good thing to re-design it for Bulldozer.
 
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#60
Unganged, while not true 4-channel, splits the dual channel 128-bit controller into two 64-bit dual channel controllers. Most users are running 64-bit memorycontrol...and for some reason, it seems to be faster than 128-bit mode. They clearly need to fix 128-bit mode. Once they do, they should be on-par, if not better, than Intel's current solutions.
If you could do it you should offer them your help ;) but i know this aint possible without redesigning whole memory concept they been stuck ever since first K7 w/ ondie full speed L2 cache design came out.

You should know why is that. Hint: Remember first Phenoms and why they had troubles It wasnt because IMC, rather because botched L3 cache behaviour ;)

Unganged mode was brought to us as benefit AMD shares same die concept for servers and desktop, and going back to 128bit "fixing it" would be unsustainably stupid move.
Only market where we could see ganged mode only parts are desktops and that means APUs. And i hope they wont do that performance wise. Thou there were already rumors about Trinity support only 128b ganged mode.
 
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#61
Great to see them redesigning the memory controller for some faster access times.

Why still no move to triple channel though?, don't see anything wrong with more memory bandwidth.(though dual channel is still sufficient)

I also hope there 8 cores and mobo's are pretty cheap, may move up to Bulldozer if they are.:)

No need for Triple channel. Performance is pretty much equal with dual vs. triple.
 
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#62
Holy thread revival Batman!