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AMD X570 Puts Out Up To Twelve SATA 6G Ports and Sixteen PCIe Gen 4 Lanes

btarunr

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AMD X570 is the company's first in-house design desktop motherboard chipset for the AM4 platform. The company sourced earlier generations of chipset from ASMedia. A chipset in context of the AM4 platform only serves to expand I/O connectivity, since an AM4 processor is a full-fledged SoC, with an integrated southbridge that puts out SATA and USB ports directly from the CPU socket, in addition to LPCIO (ISA), HD audio bus, and SPI to interface with the firmware ROM chip. The X470 "Promontory Low Power" chipset runs really cool, with a maximum TDP of 5 Watts, and the ability to lower power to get its TDP down to 3W. The X570, on the other hand, has a TDP of "at least 15 Watts." A majority of the X570 motherboards we've seen at Computex 2019 had active fan-heatsinks over the chipset. We may now have a possible explanation for this - there are just too many things on the chipset.

According to AMD, the X570 chipset by itself can be made to put out a staggering twelve SATA 6 Gbps ports (not counting the two ports put out by the AM4 SoC). A possible rationale behind this may have been to enable motherboard designers to equip every M.2 slot on the motherboard with SATA wiring in addition to PCIe, without needing switches that reroute SATA connection from one of the physical ports. It's also possible that AMD encouraged motherboard designers to not wire out SATA ports from the AM4 SoC as physical ports to save costs on switches, and dedicate one of them to the M.2 slot wired to the SoC. With the two SATA ports from the SoC out of the equation, and every other M.2 slot getting a direct SATA connection from the chipset, motherboard designers can wire out the remaining SATA ports as physical ports, without spending money on switches, or worrying about customer complaints on one of their drives not working due to automatic switching. This is an extreme solution to a rather simple problem.



The second major component of the X570 chipset is its on-die PCIe switching fabric. The chipset talks to the AM4 SoC over a PCI-Express 4.0 x4 connection (8 GB/s). The chipset has a PCIe root complex that puts out 16 downstream PCI-Express gen 4.0 lanes. This allows motherboard manufacturers to deploy two additional M.2 NVMe slots with full PCIe gen 4.0 x4 wiring, in addition to the slot wired to the AM4 SoC. The remaining lanes can be wired out as U.2 ports, a PCIe x4 (physical x16) expansion slot, and to connect other bandwidth-hungry onboard devices such as 10GbE PHYs, 802.11ax WLAN controllers, Thunderbolt 3 controllers, and USB 3.1 gen 2 controllers.

Speaking of USB, we arrive at the third big thing on the X570, integrated USB 3.1 gen 2. We learn that 3rd generation Ryzen "Matisse" SoCs put out four 10 Gbps USB 3.1 gen 2 ports. Current-generation "Pinnacle Ridge" processors put out four 5 Gbps USB 3.1 gen 1 ports in its place. The X570 chipset adds to this in a big way. Apparently, the chipset puts out a staggering eight 10 Gbps USB 3.1 gen 2 ports (not counting the ports from the SoC), without needing any external controllers. This takes the total USB 3.1 gen 2 port count on the AMD "Valhalla" platform to 12. To put this number into context, Intel Z390 chipset only puts out six USB 3.1 gen 2 ports, none directly from the processor.

AMD finally beats Intel in the PCIe budget numbers-game. The 3rd generation Ryzen "Matisse" processor puts out 24 PCIe gen 4.0 lanes. Add this to the 16 PCIe gen 4.0 lanes from the X570 chipset, and you arrive at 44 lanes (including the chipset bus). This beats the 40 lanes when you combine a "Coffee Lake Refresh" processor with a Z390 Express chipset (16 + 24). It's important to note here that Intel is still stuck with PCIe gen 3.0 on its 9th generation Core platform. The Ryzen "Picasso" APU silicon only puts out 16 PCIe gen 4.0 lanes, hence we arrive at 36 lanes.

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That's kind of a misleading headline, as there are four "native" SATA ports in the chipset, but the other eight will most likely not be implemented on a lot of boards, in favour of additional M.2 slots or PCIe x4 slots. Edit: Headline updated.
It's possible that this works similar to Intel's HSIO, which means some can be one or the other on the boards, depending on what's populated.
Looking at the boards announced so far, most higher-end boards have three M.2 slots, which means no more than four SATA ports could be used, if all M.2 slots are in use.

Also, their general purpose PCIe lanes aren't quite as many as they make out, as four from the CPU and four from the chipset are used to connect the two to each other...
I guess marketing got a bit too clever.
 
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Chipset+SoC have 12 USB 10Gbps ports and still most X570 boards dont have internal Type-C header. :mad:
But has RGB everywhere. :mad:
 
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Chipset+SoC have 12 USB 10Gbps ports and still most X570 boards dont have internal Type-C header. :mad:
But has RGB everywhere. :mad:
Got to be one expensive header...
 
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Hang on, am I reading this wrong? It seems to imply that there are only 16 PCIe lanes available from the CPU, which means that in a SLI/CF configuration you would only be able to run those cards at 8/8. Which is not an issue for current PCIe 3.0 cards that run fine with 8 lanes, but might be an issue for future cards and potentially the Radeon 5700?

GamerNexus put up a video in which they say that USB Type-C headers are much more expensive and difficult to make.
Yet we have news articles saying X570 boards are going to be supa doopa expensive... adding an extra header, especially one that significantly future-proofs the board, should be a no-brainer.
 

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Hang on, am I reading this wrong? It seems to imply that there are only 16 PCIe lanes available from the CPU, which means that in a SLI/CF configuration you would only be able to run those cards at 8/8. Which is not an issue for current PCIe 3.0 cards that run fine with 8 lanes, but might be an issue for future cards and potentially the Radeon 5700?



Yet we have news articles saying X570 boards are going to be supa doopa expensive... adding an extra header, especially one that significantly future-proofs the board, should be a no-brainer.
I think that PCIe 3.0 will be just fine for the new AMD GPUs so even if the slots are running in the 8/8 configuration there will be no downgrade because PCIe 4.0 x8 = PCIe 3.0 x16 (I think).
 

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Hang on, am I reading this wrong? It seems to imply that there are only 16 PCIe lanes available from the CPU, which means that in a SLI/CF configuration you would only be able to run those cards at 8/8. Which is not an issue for current PCIe 3.0 cards that run fine with 8 lanes, but might be an issue for future cards and potentially the Radeon 5700?
Yet we have news articles saying X570 boards are going to be supa doopa expensive... adding an extra header, especially one that significantly future-proofs the board, should be a no-brainer.
PCIe 4.0 x8 is the same bandwidth as PCIe 3.0 x16. Radeon 5700 supports gen 4.0. This is still a mainstream desktop platform. Multi-GPU is a dying technology for gaming.
 
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Hang on, am I reading this wrong? It seems to imply that there are only 16 PCIe lanes available from the CPU, which means that in a SLI/CF configuration you would only be able to run those cards at 8/8. Which is not an issue for current PCIe 3.0 cards that run fine with 8 lanes, but might be an issue for future cards and potentially the Radeon 5700?
You are aware that these are PCIe 4.0 and not 3.0 thus virtually making them the same bandwidth as "16/16 PCIe 3.0" ?
 
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editor fyi "Puts Out Up To" => "Supports"
 
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GamerNexus put up a video in which they say that USB Type-C headers are much more expensive and difficult to make.
That for case, not for motherboard. Some quality case already has 3.1 Type-C. When you start mass produce it, it will become cheaper.
If I am not wrong USB 3 internal header for case was expensive at first, but when you start to implement everywhere it becomes cheaper. Now even cheap 70$ boards has USB 3 header and so does cheap case. My 30$ case has USB 3 port.
For motherboard manufacturer, it not like you have to buy a USB 3.1 10Gbps controlar to support it, as chipset+SoC has planty of 3.1 10Gbps support.
 
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No, only one. They've messed up the block diagram with the chipset, if you compare with the one of the CPU, or at least made it really confusing.

Hang on, am I reading this wrong? It seems to imply that there are only 16 PCIe lanes available from the CPU, which means that in a SLI/CF configuration you would only be able to run those cards at 8/8. Which is not an issue for current PCIe 3.0 cards that run fine with 8 lanes, but might be an issue for future cards and potentially the Radeon 5700?

Yet we have news articles saying X570 boards are going to be supa doopa expensive... adding an extra header, especially one that significantly future-proofs the board, should be a no-brainer.
This has always been the case for Ryzen, one x16 or two x8.

And yeah, I can't imagine it's more than a $2 part so...
 
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I can see the next TR platform having 8 or 16 lanes to the chipset.
 
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The 3rd generation Ryzen "Matisse" processor puts out 24 PCIe gen 4.0 lanes. Add this to the 16 PCIe gen 4.0 lanes from the X570 chipset, and you arrive at 44 lanes.
24 + 16 = 44
Yeah! but wait!
 
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Well the 4x link to/from the chipset is not counted presumably?
 
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I think that PCIe 3.0 will be just fine for the new AMD GPUs so even if the slots are running in the 8/8 configuration there will be no downgrade because PCIe 4.0 x8 = PCIe 3.0 x16 (I think).
PCIe 4.0 x8 is the same bandwidth as PCIe 3.0 x16. Radeon 5700 supports gen 4.0. This is still a mainstream desktop platform. Multi-GPU is a dying technology for gaming.
You are aware that these are PCIe 4.0 and not 3.0 thus virtually making them the same bandwidth as "16/16 PCIe 3.0" ?
This has always been the case for Ryzen, one x16 or two x8.
Yeah I had a brainfart, mainstream platforms have always had a maximum of 16 lanes available to GPUs and bifurcate said lanes as necessary for multi-GPU allocations.
 
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I can see the next TR platform having 8 or 16 lanes to the chipset.
You could be right...

43049770_1474916195873953_6750697100406685696_n.png


The 3rd generation Ryzen "Matisse" processor puts out 24 PCIe gen 4.0 lanes. Add this to the 16 PCIe gen 4.0 lanes from the X570 chipset, and you arrive at 44 lanes.
24 + 16 = 44
Yeah! but wait!
It's actually 16+4+4 from the CPU and 8+4+4+4 from the chipset, which adds upp to 44, but 4 from the CPU and 4 from the chipset only connect to each other and are as such not "general purpose" as AMD puts it in the slides.
 
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Chipset+SoC have 12 USB 10Gbps ports and still most X570 boards dont have internal Type-C header. :mad:
But has RGB everywhere. :mad:
You mean the header that can be used to connect USB Type-C kabel for front pannel on the computer case or?
I think at least I saw one on ASUS crosshair VIII.
My Crosshair VII (x470) has one also. I am using it on my Cooler Master COSMOS C700P with USB Type-C front pannel port.

See the circled connector on image below.
 

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The Asrock ones seem to have it, PG and TC anyway.

It can be hard to see in some of the pictures, but is there.
 
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You mean the header that can be used to connect USB Type-C kabel for front pannel on the computer case or?
I think at least I saw one on ASUS crosshair VIII.
My Crosshair VII (x470) has one also. I am using it on my Cooler Master COSMOS C700P with USB Type-C front pannel port.

See the circled connector on image below.
Yes that one marked in circle.
X370/X470 only have 2 10Gps USB 3.1 port. The header one need editional cheap. Thats why some highend and midrange X370/X470 board have it
But X570 chipset have 8 10Gbps USB 3.1 port, so no extra chip needed. As a result all X570 should have at least one Type-C header. Many new X570 board dont have it which is unacceptable.
 
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ASRock Phantom gaming is more mid-level. They seem to be using it as a differentiator between the low-end and the mid and above. The low end ones (e.g. X470 Master) have two 3.0 FPH instead.

The low end X570 (if there will even be those) are not listed yet.
 

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You could be right...

View attachment 124784



It's actually 16+4+4 from the CPU and 8+4+4+4 from the chipset, which adds upp to 44, but 4 from the CPU and 4 from the chipset only connect to each other and are as such not "general purpose" as AMD puts it in the slides.
So they're double-counting the CPU<->X570 Chipset connection. I thought only data networking companies like Cisco did misleading things like that...
 
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So they're double-counting the CPU<->X570 Chipset connection. I thought only data networking companies like Cisco did misleading things like that...
Maybe just one way ...

20 useable from CPU + 16 useable from chipset = 36, but 40 seems to be going around which would be double counting once, which is kind of OK as it is doing something.

It's a bit funny/iffy though and likely due to Intel probably using this method so it needs to match up in comparison tables. Or do Intel have the "DMI" separate and not included in the lane count?

I still like the extra 4 lanes from the CPU though.
 
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