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This is a new core built upon the legacy of Bobcat -> Jaguar -> Excavator+. While, it is 15h-biased it is not a 15h core aka does not use 15h SOG. The product placement for all SoCs are aimed at competition with Zhaoxin/VIA ZX-D& ZX-E - KX-5000 & KX-6000 octo-core/quad-core and Intel's Gemini Lake/Mercury Lake quad/server(8/12/16-core).
The roadmap for AMD states a refresh number two for Bristol Ridge and Stoney Ridge for 2018. These products will be replaced by SoCs with this core. Pretty much everything in this core will be re-used in later Zen cores.
1. Scalable CCX..
This is basically a overhaul of the core complex in Zen, in which to make it more scalable. It is more optimized to go from single-core, dual-core, quad-core, hexa-core, octo-core configs. (cores = dual-core modules)
2. Flip-Flop topology..
It will be using multi-bit single phase flip-flop topology, over the single-bit dual-phase master-slave? flip-flop topology in Bulldozer -> Excavator.
3. Redesigned cache configuration...
Not much to know... so I'll wing it. I am not speculating data width(16 byte/32 byte/64 byte) or rates(how much gigabytes effective).
128 Kilobyte L0/L1 (Instruction/Data) -> 512 Kilobyte L2 -> 2 Megabyte L3 per slice of the scalable core complex.
4. High-Performance core(Excavator) to Low-power w/ (green)Server-focus core(This core)..
The "ID", the two "CL", the "FLOAT" is changed... https://images.anandtech.com/doci/10009/Slide 10 - Excavator High Level.png <== those parts.
Instruction decode for example going from 4-wide(8-wide) to 3-wide(6-wide). The execution width of the Integer/GenPurp cores moving from 4-wide to 3-wide, etc. Optimized for efficient performance, retrograde in peak performance. So, effectively the new core might run faster at same clock speeds to Excavator+. While, it won't be competing with Zen cores in performance or price.
5. Optimized for FDSOI which is complementary to FinFET..
FDSOI for budget reasons via ~40% TCO reduction for similar transistor performance, etc. This helps push the SoCs into the sub-$90 markets that were reserved for Sempron X2/Athlon X2/Athlon X4. While, supporting the same chipset as Ryzen products. FP5(+) will be shared, and AM4(+) will be shared between FDSOI and FinFET SoCs.
6. Speculative Timeline...
March-May 2018 announcement
June-August 2018 paper
September-November 2018 availability
7. Extended ALU/FPU speculation... (and area) // the exact changes are unknown, but it is in the opposite direction of Zen.
- 4-op (2 arithmatic ports and 2 logic/ld/st ports) to 3-op (3 arithmetic ports with p1 w/ load and p2 w/ store)
ALU0 => MUL/DIV/EX
ALU1 => LEA/POPCNT/EX/LD
ALU2 => BRN-JUMP/EX/ST
- FPU is up in the air... could be port of Zen's FPU or modified Excavator's FPU, or it could be something else.
Something else being a 2-wide FPU; AVX512 in both pipe0(IFMA/ER) and 1(STORE/BW/VBMI). Which is the "server-focus" comment from above is pointing at. This FPU shares its IP with the GCN CU in which most of the GPU stuff is removed and it is modified and optimized for least data movement. Least data movement is essentially a design methodology for lowest leakage from data movement. The modern GCN CU has capabilities of SIMD within SIMD via RPM. So, in a way muiltiple 128-bit or 256-bit AVX/SSE can be smooshed into a translated AVX512 op. Intriciated details are way to much for just this post.
My area calculations for the above core using Jaguar/Zen/Excavator as guides indicated ~18 mm squared per slice. 8~9.8 mm squared for ID/2-Core/FPU(AVX512) + 4~5 mm squared L2 SRAM(performance optimized SRAM) + 5~6 mm squared L3 SRAM(area optimized SRAM).
8. Miscellaneous...
- In select SKUs FDSOI SoCs might have integrated Bluetooth, Wi-Fi(Ax/Ac/N), and LTE-A. (Semi-custom laptop/tablets w/ third-party Qualcomm IP)
-
The roadmap for AMD states a refresh number two for Bristol Ridge and Stoney Ridge for 2018. These products will be replaced by SoCs with this core. Pretty much everything in this core will be re-used in later Zen cores.
1. Scalable CCX..
This is basically a overhaul of the core complex in Zen, in which to make it more scalable. It is more optimized to go from single-core, dual-core, quad-core, hexa-core, octo-core configs. (cores = dual-core modules)
2. Flip-Flop topology..
It will be using multi-bit single phase flip-flop topology, over the single-bit dual-phase master-slave? flip-flop topology in Bulldozer -> Excavator.
3. Redesigned cache configuration...
Not much to know... so I'll wing it. I am not speculating data width(16 byte/32 byte/64 byte) or rates(how much gigabytes effective).
128 Kilobyte L0/L1 (Instruction/Data) -> 512 Kilobyte L2 -> 2 Megabyte L3 per slice of the scalable core complex.
4. High-Performance core(Excavator) to Low-power w/ (green)Server-focus core(This core)..
The "ID", the two "CL", the "FLOAT" is changed... https://images.anandtech.com/doci/10009/Slide 10 - Excavator High Level.png <== those parts.
Instruction decode for example going from 4-wide(8-wide) to 3-wide(6-wide). The execution width of the Integer/GenPurp cores moving from 4-wide to 3-wide, etc. Optimized for efficient performance, retrograde in peak performance. So, effectively the new core might run faster at same clock speeds to Excavator+. While, it won't be competing with Zen cores in performance or price.
5. Optimized for FDSOI which is complementary to FinFET..
FDSOI for budget reasons via ~40% TCO reduction for similar transistor performance, etc. This helps push the SoCs into the sub-$90 markets that were reserved for Sempron X2/Athlon X2/Athlon X4. While, supporting the same chipset as Ryzen products. FP5(+) will be shared, and AM4(+) will be shared between FDSOI and FinFET SoCs.
6. Speculative Timeline...
March-May 2018 announcement
June-August 2018 paper
September-November 2018 availability
7. Extended ALU/FPU speculation... (and area) // the exact changes are unknown, but it is in the opposite direction of Zen.
- 4-op (2 arithmatic ports and 2 logic/ld/st ports) to 3-op (3 arithmetic ports with p1 w/ load and p2 w/ store)
ALU0 => MUL/DIV/EX
ALU1 => LEA/POPCNT/EX/LD
ALU2 => BRN-JUMP/EX/ST
- FPU is up in the air... could be port of Zen's FPU or modified Excavator's FPU, or it could be something else.
Something else being a 2-wide FPU; AVX512 in both pipe0(IFMA/ER) and 1(STORE/BW/VBMI). Which is the "server-focus" comment from above is pointing at. This FPU shares its IP with the GCN CU in which most of the GPU stuff is removed and it is modified and optimized for least data movement. Least data movement is essentially a design methodology for lowest leakage from data movement. The modern GCN CU has capabilities of SIMD within SIMD via RPM. So, in a way muiltiple 128-bit or 256-bit AVX/SSE can be smooshed into a translated AVX512 op. Intriciated details are way to much for just this post.
My area calculations for the above core using Jaguar/Zen/Excavator as guides indicated ~18 mm squared per slice. 8~9.8 mm squared for ID/2-Core/FPU(AVX512) + 4~5 mm squared L2 SRAM(performance optimized SRAM) + 5~6 mm squared L3 SRAM(area optimized SRAM).
8. Miscellaneous...
- In select SKUs FDSOI SoCs might have integrated Bluetooth, Wi-Fi(Ax/Ac/N), and LTE-A. (Semi-custom laptop/tablets w/ third-party Qualcomm IP)
-
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