Article on Moore's Law and 40nm Yield Problems

[Binge]

Transistor level design which lnclude Mixed Signal, Analog/RF, Embedded Memory, Standard Cell, and I/O, are the most susceptible to parametric yield issues caused by process variation.

Process variation may occur for many reasons during manufacturing, such as minor changes in humidity or tempature changes in the clean-room when wafers are transported, or due to non uniformities introduced during process steps resulting in variation in gate oxide, doping, and lithography; bottom line it changes the performance of the transistors...

to read more--

Source: http://danielnenni.com/2009/11/23/moores-law-and-40nm-yield/

I particularly enjoyed this detailed look into design and manufacturing.

 

[[I.R.A]_FBi]

Hol' a tanks

 

[eidairaman1]

TBH i think the makers should look at the older processes and refine them instead of releasing one that is smaller, as that just in turn causes more ass pain in the long run, especially when getting average and ideal yields.