Bo_Fox
New Member
- Joined
- May 29, 2009
- Messages
- 480 (0.09/day)
- Location
- Barack Hussein Obama-Biden's Nation
System Name | Flame Vortec Fatal1ty (rig1), UV Tourmaline Confexia (rig2) |
---|---|
Processor | 2 x Core i7's 4+Gigahertzzies |
Motherboard | BL00DR4G3 and DFI UT-X58 T3eH8 |
Cooling | Thermalright IFX-14 (better than TRUE) 2x push-push, Customized TT Big Typhoon |
Memory | 6GB OCZ DDR3-1600 CAS7-7-7-1T, 6GB for 2nd rig |
Video Card(s) | 8800GTX for "free" S3D (mtbs3d.com), 4870 1GB, HDTV Wonder (DRM-free) |
Storage | WD RE3 1TB, Caviar Black 1TB 7.2k, 500GB 7.2k, Raptor X 10k |
Display(s) | Sony GDM-FW900 24" CRT oc'ed to 2560x1600@68Hz, Dell 2405FPW 24" PVA (HDCP-free) |
Case | custom gutted-out painted black case, silver UV case, lots of aesthetics-souped stuff |
Audio Device(s) | Sonar X-Fi MB, Bernstein audio riser.. what?? |
Power Supply | OCZ Fatal1ty 700W, Iceberg 680W, Fortron Booster X3 300W for GPU |
Software | 2 partitions WinXP-32 on 2 drives per rig, 2 of Vista64 on 2 drives per rig |
Benchmark Scores | 5.9 Vista Experience Index... yay!!! What??? :) |
i thought w1z kinda clarified that memory bus width isn't limited by memory chips but the number of ROP's. I personally don't think they went 512-bit via ring bus for the HD 5870 as every rumor released so far has stated a 256-bit. Though i could see them using one when GT300 is released to help compete.
Largon already said that 16 memory chips is definitely needed for 512-bit memory bus, as each chip is limited to a 32-bit wide interface.
All W1z literally said was that a GPU has a number of ROP's that is directly tied to a certain bus-width memory interface... just like with a GTX 275 that has 28 ROP's and 448-bit bandwidth and a GTX 285 that has 32 ROP's and 512-bit bandwidth. But then again, Largon could be correct in that a (512-bit or 1024-bit) ringbus changes this, since ATI did 512-bit memory with only 16 ROP's and a ringbus.