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Dual-CCD Ryzen 5 5600X and Ryzen 7 5800X In the Wild

btarunr

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Certain AMD Ryzen 5 5600X and Ryzen 7 5800X processors are physically based on a dual-CCD design, according to an investigative report by Igor's Lab and Yuri "1usmus" Bubliy. The 5600X and 5800X are normally meant to be single-CCD processors owing to their core-counts. Based on the "Vermeer" multi-chip module design, the Ryzen 5000 series desktop processors use up to two 8-core CCDs to achieve their core-counts of up to 16 cores, with the 6-core 5600X and 8-core 5800X normally having just one CCD; while the 12-core 5900X and 16-core 5950X use two.

There are, apparently, some 5600X and 5800X built from dual-CCD MCMs, in which an entire CCD, although physically present on the package, is disabled. A 5600X based on a dual-CCD design is essentially a 5900X from which one of the CCDs didn't fully qualify; while the 5800X dual-CCD is a 5950X in which one such die didn't quite make the cut. There's no telling which CCD is disabled, it could be CCD 0 or CCD 1, those with CCD 0 disabled could trigger minor (benign) UI bugs with certain tuning utilities, which is how Wallossek and Bubliy discovered these chips. In any case, you're getting a 5600X or 5800X that works as advertised, and is fully covered by AMD's product warranties. Igor's Lab is investigating further into these dual-CCD 5600X and 5800X chips, and is probing the possibility of unlocking them to Ryzen 9.



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Wonder if these get the double write bandwidth advantage of dual CCD or if it's just the latency penalty.
 
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Ew no, the single biggest reason Zen3 is so good is because of the unified cache and lower latency that brings.
Splitting 6 or 8 cores over two CCDs is basically assembling a Zen2 CPU out of reject Zen3 parts, and everyone already has a Zen2.


Okay, I calmed down enough to read the second paragraph now.
I wonder why they're doing this? Can it really be cheaper to produce all CPUs the same dual-CCD way and just disable chips where one of them has too much damage to even make a 6-core?
 
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Ew no, the single biggest reason Zen3 is so good is because of the unified cache and lower latency that brings.
Splitting 6 or 8 cores over two CCDs is basically assembling a Zen2 CPU out of reject Zen3 parts, and everyone already has a Zen2.


Okay, I calmed down enough to read the second paragraph now.
I wonder why they're doing this? Can it really be cheaper to produce all CPUs the same dual-CCD way and just disable chips where one of them has too much damage to even make a 6-core?

Not sure what you are asking, they are making 5600x and 5800x's purposely with single CCD.
But they will also make 5900x's that do not work properly so they can just sell that as a 5600x when disabling one of the two CCD.

This way they can still sell that chip instead of just having to throw it all away.
 

Walrus85

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...or it might be a dummy to improve heat transfer and mechanical stability, as it was with the first generation of low core count EPYCs and TRs.
 

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Not sure what you are asking, they are making 5600x and 5800x's purposely with single CCD.
But they will also make 5900x's that do not work properly so they can just sell that as a 5600x when disabling one of the two CCD.

This way they can still sell that chip instead of just having to throw it all away.
If so.Is AMD's finished product success rate too low?
 
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Not sure what you are asking, they are making 5600x and 5800x's purposely with single CCD.
But they will also make 5900x's that do not work properly so they can just sell that as a 5600x when disabling one of the two CCD.

This way they can still sell that chip instead of just having to throw it all away.
I guess I phrased it wrong.
I was wondering if yields (and profits on higher-end parts) were such that it actually made economic sense for AMD to just produce dual-die parts and only the failed ones make a 5600X.

When I spend more than five seconds thinking about it though, that's unlikely because then you'd have a fair few chips that were 8C+6C, wasting a very valuable 8C die.
Do you think it's because AMD bin the 6-core dies before packaging two of them on the same CPU, and then discover that they didn't both survive the packaging process?
 
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Sounds to me like repurposing of chips with assembly-induced defects. That should really be a tiny proportion of the overall chip lineup, but it sure makes a lot more sense to sell a 5950X or 5900X where something goes wrong with one CCD when it's mounted to the substrate as a 5600X or 5800X than to trash the chip.

It's not like this will make any difference whatsoever when it comes to performance, so ... more of a curiosity than anything else. Good on AMD for not being wasteful, I guess?
 
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Wonder if these get the double write bandwidth advantage of dual CCD or if it's just the latency penalty.

Second CCD would be a paperweight, so neither factor would apply.

I guess I phrased it wrong.
I was wondering if yields (and profits on higher-end parts) were such that it actually made economic sense for AMD to just produce dual-die parts and only the failed ones make a 5600X.

When I spend more than five seconds thinking about it though, that's unlikely because then you'd have a fair few chips that were 8C+6C, wasting a very valuable 8C die.
Do you think it's because AMD bin the 6-core dies before packaging two of them on the same CPU, and then discover that they didn't both survive the packaging process?

It doesn't seem to make a lot of sense, because they all use the same substrate. There's not a chiplet AM4 substrate that only has connections for one CCD. Yields would have to be terrible for AMD to just be bundling dead or almost entirely dead chiplets with their CPUs.

At the end of the day, this is all speculation until 1usmus takes one of the aforementioned sus CPUs that has difficulties with CTR, and delids (ie. destroys) it to verify if it really has 2 CCDs.

And no, this isn't Renoir; having extra dead silicon doesn't help thermal dissipation at all when the chiplets aren't even physically connected.

Makes me think of the 10-core rumors, and what AMD could do if they could tweak the design to accept asymmetric CCDs. I remember reading that the 5900X and 5950X are very heavily skewed towards the better CCD in terms of clocks, power draw and load. Maybe if that second CCD is less important, it doesn't need to be binned to such high standards.
 
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Do you think it's because AMD bin the 6-core dies before packaging two of them on the same CPU, and then discover that they didn't both survive the packaging process?
I believe that the finished package undergoes some testing like temperature cycling and mechanical stressing, which kills a small percentage of chips or interconnects.

It's also likely that the chips' frequency limit, power etc. can't be determined very accurately before they're put on substrate, and electrical characteristics are affected by the substrate and socket and PCB anyway, so again, a small number doesn't make it through testing. Or they would have to be sold as 5900T, hah.

Edit: it's also possible that some I/O dies aren't fully functional or can't clock high enough, which is discovered too late in the manufacturing process.
 
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Just like those X3 chips all those years ago ?
 
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How does this even work?

AMD have to bin the best chips for the 5950X, but if one of the chiplets doesn't even work, why would they put said chiplet in a 5950X in the first place?

Or is it a way to quickly adapt to market demand? Neuter one chiplet and call it a day?
 
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At the end of the day, this is all speculation until 1usmus takes one of the aforementioned sus CPUs that has difficulties with CTR, and delids (ie. destroys) it to verify if it really has 2 CCDs.
An X-ray image should be enough and it wouldn't destroy the CPU.

However, if he or someone else successfully revives the inactive CCD and puts the processor through some tests, the results would reveal a lot about why AMD is doing this.
 
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However, if he or someone else successfully revives the inactive CCD and puts the processor through some tests, the results would reveal a lot about why AMD is doing this.
The way I see it (see above), if the disabled chiplet was defective, it wouldn't have been there on the substrate to begin with.
 
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The way I see it (see above), if the disabled chiplet was defective, it wouldn't have been there on the substrate to begin with.
There is a lot of stuff that can go wrong during assembly, e.g. the soldering of the die can be faulty. Re-soldering is expensive, as it requires manual steps, so it probably is cheaper to just disable that CCD.
 
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idk isnt this called binning? or are we back to the glue-together standard?
 
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Is latency any worse ?
 
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idk isnt this called binning? or are we back to the glue-together standard?
Binning happens before the die is packaged, and is used to determine which dice are packaged in which way for the production of various SKUs. At least that's how things normally work. If the factory is currently packaging 5950Xes, they put two top-bin dice on each substrate. If they're making 5600Xes, they use one of the die bin(s) used for that. Etc., etc. If this is true it indicates that some dual-die chips are rejected in some post-packaging QC step and then have one die disabled to make them useable rather than wasting them entirely.
 
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This feels like they're disabling perfectly good 5900X and 5950X to meet 5600X and 5800X demands.
 
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Binning happens before the die is packaged, and is used to determine which dice are packaged in which way for the production of various SKUs. At least that's how things normally work. If the factory is currently packaging 5950Xes, they put two top-bin dice on each substrate. If they're making 5600Xes, they use one of the die bin(s) used for that. Etc., etc. If this is true it indicates that some dual-die chips are rejected in some post-packaging QC step and then have one die disabled to make them useable rather than wasting them entirely.

That could be the case, maybe they found some instability in final QC stage. At this point, in may not possible to "laser-locked" them, so I bet AMD will just disable them through "BIOS". Probabilyty of unlocking them to Ryzen 9 could be higher, more so like Sempron / Athlon / Phenom era.
 
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This feels like they're disabling perfectly good 5900X and 5950X to meet 5600X and 5800X demands.
Extremely unlikely, seeing as the 5900x and 5950x have much higher margins. Given EVERYTHING is selling out, they'd rather have more high margin products this early on.

I agree with other speculation that these were former ryzen 9 parts that failed validation after manufacture being repurposed as lower end products.
 
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Is latency any worse ?
Probably not since the extra CCD is disabled, from the user's perspective it's just a 5800X or 5600X.
It's not splitting core allocation across CCD.
 
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