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Future Itanium and Xeon Processors Socket-Intercompatible

btarunr

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#1
In what could be the very first time two different machine architectures share a platform, future versions of Intel's Xeon and Itanium processors could be socket-compatible. Intel Itanium is based on the Itanium64 (IA64) machine architecture, while Xeon is x86-64 based. Intel plans to implement its common platform strategy with the next generation models of the two, that's "Kittson" Itanium, and "Haswell" Xeon.

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btarunr

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#2
Many Thanks to NHKS for the tip.
 
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#3
Can't itanium just die already?
 
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#4
I'll say it again and see if anyone complains this time 'round:

zAAm said:
Just one step closer to the merging of Itanium and Xeon architectures... ;)
 

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#5
Good to see Intel is keeping IA-64 around. IA-64 is already appealing due to it's performance advantages. I also wouldn't be surprised at all if IA-128 is the first 128-bit processor on the market. Maybe it is coming sooner rather than later.
 
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#6
i want one :) but first i want to get a xeon phi co processor :D
 
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#7
will they do that with their other product lines? I don't think so
 
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#8
I've never (personally) seen a real-world Itanium in application. Has anyone here? What was it used for? (Please, no "in theory" suggestions or links)
 
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#9
I've never (personally) seen a real-world Itanium in application. Has anyone here? What was it used for? (Please, no "in theory" suggestions or links)
That's what i wanna know can someone help Bonkers and I on this voyage to find a meaning to a 4 grand CPU such as this?
 
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#11
YOU DESERVE AN INTERNET SLAP ;) FOR WASTING 4 MINUTES OF MY TIME with that useless video, robotic voice, and absolutely NO INFORMATION that is unique to Itanium.

 
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#12
I thought Itanium was for mission critical servers that they can't just simply turn off and switch to all new tech.
 

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#13
Ia 64 vs x8664
 

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#15
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#17
In what could be the very first time two different machine architectures share a platform
Did we forget about Alpha's EV6 bus and AMD's Athlon?
 

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#18
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#19
a simple misplaced comma or period could ruin the economy of a whole country
Unfortunately, just like any processor, the Itanium cannot "beat" a mistake by the programmer or data entry person. No matter how many extra cores you throw at the problem... garbage in-garbage out.
 
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#20
That's why, for example, it doesn't use Windows as an operating system. Most Itanium systems use HP-UX. That OS has the most safety features of any out there that take the full advantage of the Itanium processors own features. Also, do you think in these fields I'm talking about people are employed by random?!? :laugh: If you can afford a Itanium system you can also afford to hire the right person to operate it. Also the main purpose of those extra cores is not what I've described, that's just an extra option, they are mainly backup blades. So if any blade in the system has some problem and can't function properly one of these extra blades steps in and takes it's place. This is at 0 cost for the end user. You never have to pay for these extra blades, they are just there in case of emergency. How's that for instant warranty replacement? :laugh:
Mmm. The availability features of the Itanium only applies to hardware, i.e. if a memory block becomes corrupt or a core fails or even when entire blades fail. Software logic errors cannot be fixed by a cpu, no matter what operating system you use.
 
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#21
This thread is turning into the deaf leading the blind, or vice versa. I refer to my post #10 for anyone who has REAL experience of REAL WORLD application, not made up conceptual nonsense.
 
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#22
Oh yes it can. I won't even begin to tell you the redundancy features HP-UX on the Itanium architecture has but here's something from Intel so you get an idea:

http://www.intel.com/content/dam/www/public/us/en/documents/guides/itanium-error-handling-guide.pdf

I will quote this from the PDF: "Operating System Error Handling: When an error is not corrected by the hardware or
firmware layers, the control is transferred to the OS. If the OS can correct the error, it
can return to the interrupted context. If the OS cannot correct the error, it can
terminate the interrupted context and switch to a new context or return to SAL with a
request to reset the system."

See? The first layer of error correction in this architecture is always the CPU. Why do you think it's so damn big? This is mainly what that extra die space is used for: error correction.
Your assumption, for example, that hardware cannot correct a software issue is so totally wrong that I didn't even want to address it in length. Know this though: there ARE people who worked on these systems or helped build these systems and I'm one of them. I was not an operator or programmer, I actually configured these systems and helped design data centers around them. Now this wasn't my main specialty, I was mainly specialized in storage systems but some of my clients wanted Itanium systems to control them so yeah I used to configure smaller Itanium based systems on a regular basis, also larger ones on occasion. I am quite familiar with this architecture and I'm not speaking out of thin air here...
You're misunderstanding the meaning of the phrase "logic error". It's different from an insertion or deletion error that can be corrected with error detection and correction (ECC) methods.

If I (as a computer engineer) mean to program a CPU to calculate 1 + 1 but I accidentally program it to calculate 1 + 2, that's a logic error. The CPU will NEVER be able to correct it (unless it's some kind of advanced AI that can predict what I MEANT to program :rolleyes: ) and will give an answer of 3 regardless.

If however I program it correctly to calculate 1 + 1 and it gives an answer of say 405,353, an insertion or deletion error occurred somewhere in memory or cache. This kind of error can be detected and corrected by the CPU or O/S through checksums, parity bits and coding. That PDF you linked to just states that the Itanium has a number of ECC levels to ensure that even entire blocks of insertion/deletion errors can be corrected in memory, cache, bus etc. Regardless, it will still never be able to correct a logic error.

What HP-UX does is software ECC on top of the already significant hardware ECC present in the Itanium. So it will use additional parity information to correct errors that were left uncorrected by the CPU.
 
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#23
does this ecc have anny use in pc's ? or only usefull in worstations/servers ?
 
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#24
does this ecc have anny use in pc's ? or only usefull in worstations/servers ?
It would have a use, but ECC takes up a lot of room in the CPU and memory controllers, which makes the CPU more expensive (you can fit less chips on a wafer). For desktop PC's, an application crash due to a hardware error would not be that bad in comparison (you might lose your current Word document progress for example), so it's usually not implemented to save costs.

For mission critical use though, a crash might amount to millions of dollars in lost revenue. Also, hardware such as memory and cache has reached pretty decent reliability figures so the advanced ECC features found in Itanium at CPU and memory level is usually not needed for desktop applications.

Error detection IS used in other desktop systems though, ex. Network Ethernet frames are sent with parity information to ensure the packet arrives without errors. I believe the PCI-Express standard also utilizes some primitive ECC features in normal operation - at least to detect errors if not correct them.
 
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#25
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