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High‑NA EUV lithography comes with a crazy $380 million price tag, but it can actually cut overall production costs in the right situations. At the SPIE Advanced Lithography and Patterning conference in February 2025, IBM researchers in Veldhoven revealed that one high‑NA exposure runs about 2.5x the cost of a standard low‑NA shot. That seems steep, yet High‑NA's real strength shows up when it replaces complicated multi‑patterning processes. SemiAnalysis had predicted last year that High‑NA would not become cost‑effective until around 2030, largely because higher dose requirements slow down throughput on the trickiest layers. However, after reviewing IBM's new data, the firm adjusted its outlook. Their model confirms that sticking with Low‑NA double patterning for two-mask sequences remains the cheapest path.
On the other hand, once you need three or more Low‑NA masks, switching to a single High‑NA pass starts to pay off. In fact, for a four‑mask self‑aligned litho‑etch flow, High‑NA can reduce total wafer cost by roughly 1.7-2.1x compared to using Low‑NA multi‑patterning. One big reason fabs are interested is that fewer exposures mean simpler process flows. You cut down cycle time and lower the chance of overlay mistakes. Still, SemiAnalysis warns that a simpler flow does not automatically mean lower expense in every case. Looking at Intel 14A, it turns out only a few critical metal layers at the 14A node hit the sweet spot where High‑NA's higher per‑shot cost is outweighed by ditching multiple masks.
Intel is the only major foundry so far to announce plans for High‑NA in volume production, focusing on those key A14 layers. Meanwhile, ASML is working on larger 6 × 12‑inch masks that could boost throughput and cut stitching overhead. To map out their next‑generation nodes, chipmakers must weigh exposure counts, tool speed, and advances in mask and resist technology before deciding if High‑NA is worth the investment. Intel has currently processed 30,000 wafers on its trial run of the 14A node, all made with Twinscan EXE:5000 High-NA tool from ASML. By the time the 14A node reaches high-volume production, we will have final information on the viability of High-NA in the HVM environment.
View at TechPowerUp Main Site | Source
On the other hand, once you need three or more Low‑NA masks, switching to a single High‑NA pass starts to pay off. In fact, for a four‑mask self‑aligned litho‑etch flow, High‑NA can reduce total wafer cost by roughly 1.7-2.1x compared to using Low‑NA multi‑patterning. One big reason fabs are interested is that fewer exposures mean simpler process flows. You cut down cycle time and lower the chance of overlay mistakes. Still, SemiAnalysis warns that a simpler flow does not automatically mean lower expense in every case. Looking at Intel 14A, it turns out only a few critical metal layers at the 14A node hit the sweet spot where High‑NA's higher per‑shot cost is outweighed by ditching multiple masks.
Intel is the only major foundry so far to announce plans for High‑NA in volume production, focusing on those key A14 layers. Meanwhile, ASML is working on larger 6 × 12‑inch masks that could boost throughput and cut stitching overhead. To map out their next‑generation nodes, chipmakers must weigh exposure counts, tool speed, and advances in mask and resist technology before deciding if High‑NA is worth the investment. Intel has currently processed 30,000 wafers on its trial run of the 14A node, all made with Twinscan EXE:5000 High-NA tool from ASML. By the time the 14A node reaches high-volume production, we will have final information on the viability of High-NA in the HVM environment.
View at TechPowerUp Main Site | Source
