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Intel Haswell Pics

T4C Fantasy

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#1
here is some pics of the haswell chip

Features carried over from Ivy Bridge
A 22 nm manufacturing process.
3D tri-gate transistors (Ivy Bridge processors and onwards).
A 14-stage pipeline (since the Core microarchitecture).
Mainstream up to quad-core.
Native support for dual channel DDR3.
32KB data + 32KB instruction L1 cache per core.
256KB L2 data cache per core[8] and up to 32MB L3 cache shared by all cores.

Confirmed features
Advanced Vector Extensions 2 (AVX2) instruction set, also called Haswell New Instructions (includes gather, bit manipulation, and FMA3 support).
New sockets — LGA 1150 for desktops and rPGA947 & BGA1364 for the mobile market.
Intel Transactional Synchronization Extensions (TSX).
Direct3D 11.1 and OpenGL 3.2 graphics unit

Expected features
32 nm PCH.
A new cache design.
support for Thunderbolt technology.
There will be three versions of the integrated GPU: GT1, GT2, and GT3. According to vr-zone, the fastest version (GT3) will have 20 execution units (EU).[15] Another source, SemiAccurate, however says that the GT3 will have 40 EUs[16] with an accompanying 64MB cache on an interposer. Haswell's predecessor, Ivy Bridge, has a maximum of 16 EUs.
New advanced power-saving system.
Base clock (BClk) increase to 133 MHz.
128 bytes cache line.[citation needed]
Execution trace cache will be included L2 caching design.
Fully integrated voltage regulator, thereby moving another component from the motherboard onto the CPU.
25, 37, 47, 57W TDP mobile processors.
77/65/55/45/35W and ~ 100W+(high-end) TDP desktop processors.
15W TDP processors for the Ultrabook platform (multi-chip package like Westmere).
 

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#2
If this is haswell what can we derive from this picture?
 

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#3
If this is haswell what can we derive from this picture?
we know what moves they are making with the chip, more components more efficiency and innovation...
 
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#4
we know what moves they are making with the chip, more components more efficiency and innovation...
Are they not always trying to do that? Maybe if you or someone could give a specific example, like this little thing here is new and does... I am far from a computer engineer. I do see that there is all those little solder prong things that are new. What are those? It is the same size as ivy which I guess is because the same 22nm process.

I feel like I sounding to negative and overly skeptical, when I am just skeptical and curious.
 

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#5
Are they not always trying to do that? Maybe if you or someone could give a specific example, like this little thing here is new and does... I am far from a computer engineer. I do see that there is all those little solder prong things that are new. What are those? It is the same size as ivy which I guess is because the same 22nm process.

I feel like I sounding to negative and overly skeptical, when I am just skeptical and curious.
Features carried over from Ivy Bridge
A 22 nm manufacturing process.
3D tri-gate transistors (Ivy Bridge processors and onwards).
A 14-stage pipeline (since the Core microarchitecture).
Mainstream up to quad-core.
Native support for dual channel DDR3.
32KB data + 32KB instruction L1 cache per core.
256KB L2 data cache per core[8] and up to 32MB L3 cache shared by all cores.

Confirmed features
Advanced Vector Extensions 2 (AVX2) instruction set, also called Haswell New Instructions (includes gather, bit manipulation, and FMA3 support).
New sockets — LGA 1150 for desktops and rPGA947 & BGA1364 for the mobile market.
Intel Transactional Synchronization Extensions (TSX).
Direct3D 11.1 and OpenGL 3.2 graphics unit

Expected features
32 nm PCH.
A new cache design.
support for Thunderbolt technology.
There will be three versions of the integrated GPU: GT1, GT2, and GT3. According to vr-zone, the fastest version (GT3) will have 20 execution units (EU).[15] Another source, SemiAccurate, however says that the GT3 will have 40 EUs[16] with an accompanying 64MB cache on an interposer. Haswell's predecessor, Ivy Bridge, has a maximum of 16 EUs.
New advanced power-saving system.
Base clock (BClk) increase to 133 MHz.
128 bytes cache line.[citation needed]
Execution trace cache will be included L2 caching design.
Fully integrated voltage regulator, thereby moving another component from the motherboard onto the CPU.
25, 37, 47, 57W TDP mobile processors.
77/65/55/45/35W and ~ 100W+(high-end) TDP desktop processors.
15W TDP processors for the Ultrabook platform (multi-chip package like Westmere).
 
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#6
Thanks. Now a benchmark... lol
 

T4C Fantasy

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#7
Thanks. Now a benchmark... lol
yeeaaah... its not 2013 yet... that chip was just a demo the product may or may not be finalized but we will definetly not see benchmarks until it becomes available to testers.
 

T4C Fantasy

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#9
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#10
if it's all on one die, how can the pch be 32nm?
I thought it was weird that there was a 32nm on a 22nm cpu. I didn't say anything because I don't know what a pch is. So pch?
 
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#11
is that secondary chip structure (on the haswell), present on ivybridge ,top left , looks to have a lot of tracks going to it , could be rastor output or something im not sure??.
 
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#12
nvm, it appears a pch is a southbridge, which is still offdie. At least there will be lower power consumption this time around. Stupid how not all ports are usb3
 

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#13
is that secondary chip structure (on the haswell), present on ivybridge ,top left , looks to have a lot of tracks going to it , could be rastor output or something im not sure??.
ive noticed theres alot more components on teh haswell chip and usuing a different material, looks like ivy bridge is using silver or aluminum
 
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#15
1150 is so close to 1155 just like 1155 was so close to 1156. Will our lga 1155 cpu coolers work on this?
If it is so close, why do we need a new socket?
 
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#16
1150 is so close to 1155 just like 1155 was so close to 1156. Will our lga 1155 cpu coolers work on this?
If it is so close, why do we need a new socket?

what you needs got nothing todo with it, intels pockets are what matters is it not, in all honesty though they do seem to make interconnect changes each time as far as i can see, id however argue that if they wanted to they could easily make them more future proof,,,,,in the extreme, 1 socket for all and so could amd for that matter

i mean if you think about it they could do a mega pin chip with a lot of pins unused on some processors it is mearly a pin package after all and could be standardized better then it is within brands