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Intel Readies Atom "Grand Ridge" 24-core Processor, Features PCIe 4.0 and DDR5

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You will remember it, because, it was true : Atom, for nearly everybody is associated with very low-end CPU. And people agreed, that if were planning on upgrading it, they should rename it.
Like i7 are associated with high-end public CPU.
Like ARM is associated with highly parallelized tasks (but slower).
Like Power 8 processors are associated with highly scalable systems.

Intel chose not to take the name down and kept it in their roadmap.


If I tell you : "you have an i7 last gen" you know what to expect.
If I tell you : "you have an Atom last gen" you have no clue what to expect.
That's the problem. Call it AtomPhi or AtomFoo, I really don't care, but just call it something else so we know a bit without looking into specs and follow the roadmap of each one.
You are making assumptions about the way everyone thinks. Not everyone thinks like you do, nor arrives at the same conclusions.
 
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In order execution is best for situations where the task being executed needs to be finished without interruption, typically meaning an RTOS which has its own scheduler that controls which tasks have priority and are going to be executed. So whatever is put in the pipeline finishes in this model - before something else jumps in front of it and thus pre-empts the scheduler and makes the system less predictable. The correct phrase is "Highly Deterministic" meaning - very predictable and repeatable low-latency performance.

Modern general purpose CPUs like Intel / AMD make are out of order systems, meaning what is being processed can be unloaded and a different 'thread' loaded in order to keep the pipelines full. In the aggregate it is faster, but it also makes it somewhat unpredictible what is going to happen to any specific operation. i.e., it's less deterministic. If this system were say, controlling the drive by wire system in your car, you might want it to be deterministic. Same if it's running a production line in a billion dollar facility.

Now, that is probably outside the normal use case for a 24 core version of this chip though. I'm just saying that predictable in order execution systems have a place, and that's what the Atom is.

I hate to contradict such a well written post... but...

Tremont (and probably Gracemont) is out-of-order. https://software.intel.com/content/...4-ia-32-architectures-optimization-manual.pdf

1597151831856.png


You can see the renaming registers, as well as the new dual-decoder structure of Tremont. Two decoders operate out-of-order (!!) on this architecture.

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EDIT: I did a bit of research into this architecture. It seems like the point is to be a frontend for the Diamond Mesa chip (https://www.intel.it/content/www/it...c/easic-devices/diamond-mesa-soc-devices.html).

Diamond Mesa will perform the heavy-work associated with routing or something. I don't really know. But the Atom is just there to interface with the ASIC. As such, the Atom doesn't really need to be fast, or realtime, at all. Its just Intel's lowest-energy chip. It does make me wonder why 24-cores are needed though.
 
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Looks like you're correct, since Silvermont Atom has been out of order.

However, what I described about the need for predictability is true, and that out of order execution makes the processor less predictable is also true. So to use any Atom past Silvermont, an embedded system would have to overcome that, or accept a certain percentage fault rate. This means that in many embedded control applications, Atom isn't the best - or at least is going to be difficult to get to fit into these scenarios.

There are many articles and papers on this.


"Furthermore, hardware used in real-time systems is steadily becoming more complex, including advanced computer architecture features such as caches, pipelines, branch prediction, and out-of-order execution. These features increase the speed of execution on average, but also makes the timing behavior much harder to predict, since the variation in execution time between fortuitious and worst cases increase. "

"Processor instruction timing has been getting increasingly variable over time, as features improving average-case performance and overall throughput are invented and put in use. Typically, performance improvements are achieved using various speculation and caching techniques, with the effect that the span between best-case and worst-case times increase. "
 
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