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Intel Reveals Details of Next-Generation High-Performance Computing Platforms

btarunr

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#1
At SC11, Intel Corporation revealed details about the company’s next-generation Intel Xeon processor-based and Intel Many Integrated Core (Intel MIC)-based platforms designed for high-performance computing (HPC). The company also outlined new investments in research and development that will lead the industry to Exascale performance by 2018.

During his briefing at the conference, Rajeeb Hazra, general manager of Technical Computing, Intel Datacenter and Connected Systems Group, said that the Intel Xeon processor E5 family is the world’s first server processor to support full integration of the PCI Express 3.0 specification**. PCIe 3.0 is estimated** to double the interconnect bandwidth over the PCIe* 2.0 specification** while enabling lower power and higher density server implementations. New fabric controllers taking advantage of the PCI Express 3.0 specification will allow more efficient scaling of performance and data transfer with the growing number of nodes in HPC supercomputers.

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#2
:laugh: larrabee lives!
 
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#3
LOL @ the guy holding "Knights Corner" chip in front of a high end wine rack.
 
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#5
Nice* press** release***
 
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#6
Wow, so many details
 
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#7
now your folding badge reminded me - i wonder how crazy ppd numbers could one of these fold?
 
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#8
So let me get this straight. Supercomputing companies get access to Sandy Bridge two months before the public and are guaranteed PCIE 3.0?

Is Knight's Corner still using the same updated P54C cores that Knight's Ferry used?

Anyone notice that in the comparison in which E5 was 2.1x faster than 5600 the 5600 platform had HyperThreading off?
 
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#11
Supports x86? Great! But does it support sse2,3,4,AVX, AES-NI, etc? If not, then it will be another Itanium and people might as well write their code for cuda/stream and use AMD and Nvidia's graphics solutions which provide much greater performance per density.
 
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#12
Supports x86? Great! But does it support sse2,3,4,AVX, AES-NI, etc? If not, then it will be another Itanium and people might as well write their code for cuda/stream and use AMD and Nvidia's graphics solutions which provide much greater performance per density.
The whole chip is programmable. Create your own instruction set from scratch (possible, not probable). This sounds like a perfect match to OpenACC