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Intel "Sapphire Rapids" Xeon Processor Could Feature Up To 80 Cores: New Leak

btarunr

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Intel's upcoming Xeon "Sapphire Rapids" enterprise processor come come with CPU core-counts as high as 80, according to the latest round of photo-leaks. An earlier article predicted the chip cram up to 56 cores alongside on-package HBM. The processor reportedly features up to 80 cores, spread across four 20-core chiplets. Unlike on the latest AMD EPYC processor, there doesn't appear to be a centralized I/O controller die. This particular processor is based in the LGA4189 package, which features additional pins compared to the LGA4577-X socket from the 56-core leak. The newer socket has additional pins that enable next-gen I/O, which include PCI-Express Gen 5.0, and CXL 1.1 interface.



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ixi

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20 chiplets O_O, that is alot. I wonder, what is happening with latency.
 
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20 chiplets O_O, that is alot. I wonder, what is happening with latency.
They are chiplets with 20-cores each, not 20 of said chiplets. :roll:
There are only 4 of them as shown in the image.
 

ixi

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They are chiplets with 20-cores each, not 20 of said chiplets. :roll:
There are only 4 of them as shown in the image.


You are right, sir! Re-read it again and yes, 4 chiplets. But still, I wonder what is the latency. :D. Will intel have better latency or worse than AMD?
 
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You are right, sir! Re-read it again and yes, 4 chiplets. But still, I wonder what is the latency. :D. Will intel have better latency or worse than AMD?
The way the chiplets are so closely packed together could be to minimize the trace length for the interconnects.
At high frequencies the physical distance matter for propagation delay and signal integrity. That is the time and distance the electrons have to travel matters.
So Intel might be trying to keep latency low as their architecture tends to be.
 
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intel found the bottle of glue
 
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What chiplets? They are more like 4 CPUs glued together next to each other.
CPUs that are build for use in quad socket systems.
 
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What chiplets? They are more like 4 CPUs glued together next to each other.
CPUs that are build for use in quad socket systems.
It'd be basically four CPUs glued together, though Intel leaks don't make any sense at the moment.
 
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"This particular processor is based in the LGA4189 package, which features additional pins compared to the LGA4577-X socket from the 56-core leak."

I think you got these packages backwards as the 4189 - 5 was rumoured to be up to 56 Cores for Ice Lake, and i'm not sure how LGA 4189 can have more pins than LGA 4577.
 

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You are right, sir! Re-read it again and yes, 4 chiplets. But still, I wonder what is the latency. :D. Will intel have better latency or worse than AMD?
dont worry, i read it wrong like you did as well

yet on re-reading, its all worded correctly our brains are just bad
 
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I thought Intel despise glue chiplet now they using it? Wonder if they're still clinging to core to core latency advantages :rolleyes:
 
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Unconfirmed leaks are nice to speculate about but not worth the timesink talking about.
 
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"This particular processor is based in the LGA4189 package, which features additional pins compared to the LGA4577-X socket from the 56-core leak."

I think you got these packages backwards as the 4189 - 5 was rumoured to be up to 56 Cores for Ice Lake, and i'm not sure how LGA 4189 can have more pins than LGA 4577.

Came here to post the same comment.
 
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So basically Zen 1.0 level, where the chiplets communicated with each other akin to UPI / Hypertransport.

This is a natural 1.0 chiplet solution. AMD's Zen 2 introduced the I/O die, which has performed far better than I expected. NVidia's multi-GPU solution (NVLink / NVSwitch) also uses an I/O die of sorts, so the switched "central" I/O design is probably the superior design.

Still, given how UPI / Hypertransport was already designed for inter-chip communication (aka: without an I/O die and just wiring up the chips together), it makes sense to start with this design first. In both cases, latency will go up compared to a single die solution, but I think Zen2 / NVidia NVSwitch has proven that latency can go up by dramatic amounts and yet we can still write software that works with that kind of latency.

---------

Laptops / Desktops are traditionally single-core programmed. But if more and more code (aka: video games or other software) keep getting better and better at latency hiding / multicore compute, maybe the processor of the future will have even higher latency. Or maybe, Apple M1 / Cell phones will snap us back into traditional, lower-latency architectures.
 
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I shudder to think how much that chip is going to cost!
 
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I shudder to think how much that chip is going to cost!
Threadripper 3990X - 64C/128T, MSRP $4000
Xeon 9180P (guess on name) - 80C/160T?, MSRP $15000
 

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Moar cores!

Remember when people laughed at AMD for moar cores?
 
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Threadripper 3990X - 64C/128T, MSRP $4000
Xeon 9180P (guess on name) - 80C/160T?, MSRP $15000
A better comparison would be the EPYC 64 core flagship CPU (around $7,000?) as it is enterprise and server grade chip, Threadripper is HEDT chip.
Moar cores!

Remember when people laughed at AMD for moar cores?
Intel isn't laughing now, they have seen the light! Thank you AMD for giving us more for less!
 
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Benchmark Scores are good
A better comparison would be the EPYC 64 core flagship CPU (around $7,000?) as it is enterprise and server grade chip, Threadripper is HEDT chip.
Couldn't remember the naming scheme of Epyc chips, so I used a close equivalent.
 
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Couldn't remember the naming scheme of Epyc chips, so I used a close equivalent.
No worries, happens to all of us at one point.
 

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