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Intel Sunny Cove Successor Significantly Bigger: Jim Keller

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Sunny Cove is codename for Intel's first truly new performance CPU core design since "Skylake," and made its debut with the company's 10 nm "Ice Lake" processors, packing the first tangible IPC increase in years. VLSI guru Jim Keller is leading the effort to build Intel's future CPU core designs, and dropped a big hint on what to expect, speaking at a gathering in U.C. Berkeley. It's unclear which specific core Keller is referring to. The immediate successor to "Sunny Cove" is codenamed "Willow Cove," and Intel's own public sketch hints at an incremental upgrade over Sunny Cove, with faster caches and process-level optimization. It's only with "Golden Cove," slated for 2021, that Intel speaks of its next round of IPC increases (dubbed "ST perf"). It's plausible that Keller is referring to this core since a 2021 launch would fit better with a 2018-19 design phase.

In his talk, Keller describes Intel's next big CPU core as being "significantly bigger" than "Sunny Cove," with its 800-wide instruction window, and "massive" data- and branch-predictors, to put Intel back on a linear performance growth trajectory between generations. Keller also commented on this being a "mindset change" at Intel, which over the past decade, only delivered minor IPC increments between generations, and focused on other areas, such as efficiency. In stark contrast, through the 1990s and 2000s, Intel delivered IPC leaps between generations, such as the one between "Netburst" and "Conroe," and onwards to "Nehalem." These were in-part helped by rapid process advancements that slowed in the 2010s as Intel approached the sub-10 nm scale.



The video presentation by U.C. Berkeley follows.


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Jim motherffing Keller, back at it again
 
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Why just now they (Intel) rejoining the inovative part of the scene , as ever since "Skylake" , it's as if Intel was in retirement cashing pension coupons or viewed another way , a multy year sabbatical.
So , in another parallel universe, I am safekeeping my 2 entry-level Skylake cpu's one being a Pentium spec whilst the other is a Celeron spec , having them donated to museums all the while story talking my children/grandchildren on how the x86 cpu's "war's" were "fought" and reminiscent of the era's when Intel was top dog in most of those , until "Ivy-Lake" .

"Good night and faa iuu"
 

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As usual from Intel nowadays: more projections, more PR slides, more announcements. Wake me up when the products are on shelves instead.
 
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As usual from Intel nowadays: more projections, more PR slides, more announcements. Wake me up when the products are on shelves instead.

And Jim has lowered himself to marketing for Intel lol

All I hear is inadequacy like a truck jacked up 2ft.
This is so far away that newborns will be running around asking where it's at lol
 
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Why just now they (Intel) rejoining the inovative part of the scene , as ever since "Skylake" , it's as if Intel was in retirement cashing pension coupons or viewed another way , a multy year sabbatical.
There have been meaningful architectural upgrades in Intel CPUs. Haswell and Skylake are OKish updates. Since Skylake they have been stuck at 14nm which is their main problem. They seem to have architectures ready but 10nm was intended to be in full production in 2016. This did not happen and Intel has been limping along on Skylake and 14nm ever since.

We can speculate why they have not backported for example Sunny Cove to 14nm but there are good technical reasons why this would not be viable. It is bigger which also means hotter. Backporting will take a year or year and a half which Intel architecture engineers thought was reasonable timeframe to get 10nm running. That did not pan out.
 

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Welp, Intel is slated to make a come back in 2021. AMD better milk it while they can.

Honestly, it all makes sense. Intel can't move to 10 nm because the architecture...which dates back to Nehalem...isn't meant for it. Intel needed to think outside of the box with a new architecture that can transition to 10 nm and beyond. That's what Keller does: new architectures optimized for new nodes.

And Jim has lowered himself to marketing for Intel lol
I think he gave this talk at U.C. Berkley to excite the next generation of electrical engineers. There's a whole lot of doom and gloom out there about advancing nodes and Keller is really the only one publicly challenging it.


Edit: I wouldn't be surprised if what Jim Keller has been working on is forked from *Cove products (as in parallel to or after Golden Cove). Keller does the architectural work then leaves. It's handed over to production at that point which can take a long time to improve and test. To hire Keller and then limit him to only modifying your existing cores--it's a waste of effort. Whatever he's working on is going to be like the jump to Conroe or Nehalem.
 
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Welp, Intel is slated to make a come back in 2021. AMD better milk it while they can.

Honestly, it all makes sense. Intel can't move to 10 nm because the architecture...which dates back to Nehalem...isn't meant for it. Intel needed to think outside of the box with a new architecture that can transition to 10 nm and beyond. That's what Keller does: new architectures optimized for new nodes.


I think he gave this talk at U.C. Berkley to excite the next generation of electrical engineers.

With what? More quad cores?
 
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Honestly, it all makes sense. Intel can't move to 10 nm because the architecture...which dates back to Nehalem...isn't meant for it. Intel needed to think outside of the box with a new architecture that can transition to 10 nm and beyond.
Intel has architecture ready for 10nm but 10nm manufacturing itself is missing. Cannon Lake was die shinked Skylake (that failed in manufacturing, not architecture or design) and Sunny Cove/Ice Lake was intended to be updated architecture on 10nm but it has been waiting on manufacturing for a couple years now.
 

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Architecture and process manufacturing go hand in hand. Skylake and sons are effectively a square peg Intel has been trying to ram into a round hole (10nm process) for three years. Splash a dose of insanity on top (doing the same thing expecting different results) and that's pretty much where Intel was, is, and will be until the chips Keller are working on reaches the market.

Remember that Nehalem is almost 11 years old now and was originally designed for 45 nm process. They've been iterating on the same fundamental architecture for far too long. Tick-tock...you eventually got to ring the chime ushering in a new tick-tock.
 
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Architecture and process go hand in hand. Skylake and sons are effectively a square peg Intel has been trying to ram into a round hole (10nm process) for three years. Splash a dose of insanity on top (doing the same thing expecting different results) and that's pretty much where Intel was, is, and will be until the chips Keller are working on reaches the market.
No they don't. There are some parts of architecture that need to be designed for the intended manufacturing process but it is not strictly tied to one. Just look at Zen or GPUs that are manufactured in different fabs - for example Zen in GF and TSMC, GPUs in TSMC but also in Samsung or GF. Due to in-house foundries Intel has process and architecture more closely tied together but moving the architecture to another manufacturing process is not difficult in itself but it is pretty time-consuming (and expensive).

Keller's main area of expertise is architecture, not manufacturing. While he probably has enough power to impact manufacturing that is a whole different area.
 

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No they don't. There are some parts of architecture that need to be designed for the intended manufacturing process but it is not strictly tied to one. Just look at Zen or GPUs that are manufactured in different fabs - for example Zen in GF and TSMC, GPUs in TSMC but also in Samsung or GF. Due to in-house foundries Intel has process and architecture more closely tied together but moving the architecture to another manufacturing process is not difficult in itself but it is pretty time-consuming (and expensive).
Zen was designed for 14nm. GCN was designed for 28nm. GCN resulted in a power hungry monster at 7nm. RDNA establishes a new baseline for AMD that will likely translate well to 5nm.

Hopefully not monolithic dies. Chiplets are the future.
Intel will make a comeback for sure but people think AMD will stay still and are unable to fight back in 2021.
The thing that's going to bite Intel in the ass is that their process tech has fallen behind. They'll need something better than 10 nm to answer AMD in 2021 when AMD will probably start shipping some 5 nm products.
 
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Hopefully not monolithic dies. Chiplets are the future.
Intel will make a comeback for sure but people think AMD will stay still and are unable to fight back in 2021.

Yep, cores are about maxed, now. There's no point spending wafers and power budget on that (software is so far behind). Use the coming shrinks to widen everything and add lots of cache.

Zen 3 is already rumored to start that. If true, then you can expect a doubling down on that.

And Intel will still have dick for manufacturing.
 
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A bigger core needs, I guess, smaller manufacturing. So, this is nice and it will push AMD to NOT stop innovating, but if Intel's 7nm ends up like the 10nm mess, those cores are going to end up in dual and quad core models, like with today's 10nm products. And it is difficult to trust Intel. I mean TSMC got over their 20nm fiasco in no time. Intel is hitting it's head on a wall for 4 years. Can someone really trust them with 7nm? If they get it right from the beginning maybe. If they face problems...
 
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Things such as huge instruction windows and complicated branch prediction logic have proven to rear their head into extremely poor inefficiencies in terms of power and area relative to the speedup they provide.

It's a bad trade-off that only gets worse the more you do it, ILP is bound to hit a hard limit and no matter how much you dedicate logic to extract it you will reach a point where it simply wont give any advantage whatsoever. Moore's law is dying and these nuclear options that Keller is putting forward are proof of it.

Just look at Zen or GPUs that are manufactured in different fabs - for example Zen in GF and TSMC, GPUs in TSMC but also in Samsung or GF.

No, that's exactly the point. They are manufactured in different fabs precisely because they have been designed with that specific fabrication process in mind.
 
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Architecture and process manufacturing go hand in hand. Skylake and sons are effectively a square peg Intel has been trying to ram into a round hole (10nm process) for three years. Splash a dose of insanity on top (doing the same thing expecting different results) and that's pretty much where Intel was, is, and will be until the chips Keller are working on reaches the market.

Remember that Nehalem is almost 11 years old now and was originally designed for 45 nm process. They've been iterating on the same fundamental architecture for far too long. Tick-tock...you eventually got to ring the chime ushering in a new tick-tock.

I would say there is a sum of unfortunate mishaps so both you are right. This quite old news BTW they did that already in Haifa. Raja had more interesting retweets before. Jim and Tim did together keynotes also last year...

132961
 
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Zen was designed for 14nm. GCN was designed for 28nm. GCN resulted in a power hungry monster at 7nm. RDNA establishes a new baseline for AMD that will likely translate well to 5nm.
Zen2 is still Zen with minor improvements and it seems to be fine in 7nm.
GCN resulted in a power hungry monster at 14nm (and 28nm) as well :)
 
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Zen2 is still Zen with minor improvements and it seems to be fine in 7nm.
GCN resulted in a power hungry monster at 14nm (and 28nm) as well :)

GCN is power efficient at the correct clocks/V. Unfortunately, the design did not leave enough clock to compete effectively. It's like running zen 1 at 4.2/4.3 GHz.

The complete lack of binning really exacerbated it.
 
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Hopefully not monolithic dies. Chiplets are the future.
In enterprise, servers, manycore CPUs definitely.

On desktop? If manufacturer is willing to do multiple dies, monolithic should have the potential to be better. Die sizes were reasonable for 8 cores on 12/14/16nm - Zen/Zen+ at ~200mm^2 and 9900K at ~175mm^2. From 12nm to 7nm there is 40-60% area reduction. Chiplets may come into play for other reasons though - some reports on Intel 10nm failures had things to say about IO and AMD has stated IO does not scale down well any more.

It will be interesting to see what AMD will do in terms of APUs next time around. Raven Ridge and Picasso are both monolithic.
 
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In enterprise, servers, manycore CPUs definitely.

On desktop? If manufacturer is willing to do multiple dies, monolithic should have the potential to be better. Die sizes were reasonable for 8 cores on 12/14/16nm - Zen/Zen+ at ~200mm^2 and 9900K at ~175mm^2. From 12nm to 7nm there is 40-60% area reduction. Chiplets may come into play for other reasons though - some reports on Intel 10nm failures had things to say about IO and AMD has stated IO does not scale down well any more.

It will be interesting to see what AMD will do in terms of APUs next time around. Raven Ridge and Picasso are both monolithic.

AMD was able to kill "multiple birds with one stone" by sharing the processing chiplets between enterprise workstation, server and desktop CPUs. They can make a lot of them cheaply, bin appropriately and reap the benefits of economy of scale. Since they are smaller the defect ratios are lower than monolithic. Not to mention research and tooling costs.

For the next gen APU I'd like to see a chiplet with combo IO+GPU die. It would make sense since the IMC is on the IO die already.
 
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When you fabricate your cores on 14nm, it will bigger than 10nm.
 

ppn

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In enterprise, servers, manycore CPUs definitely.

On desktop? If manufacturer is willing to do multiple dies, monolithic should have the potential to be better. Die sizes were reasonable for 8 cores on 12/14/16nm - Zen/Zen+ at ~200mm^2 and 9900K at ~175mm^2. From 12nm to 7nm there is 40-60% area reduction. Chiplets may come into play for other reasons though - some reports on Intel 10nm failures had things to say about IO and AMD has stated IO does not scale down well any more.

It will be interesting to see what AMD will do in terms of APUs next time around. Raven Ridge and Picasso are both monolithic.

40% area reduction is more accurate, we can drop the 60% number entirely.

Zen is 44mm^2 per CCX (60 mm^2 when L3 is doubled), and ZEN2 is 38 mm^2 L3 included, so we have 38/60 or 36% reduction.
this is Not 7nm, more like 10nm shrink.
 
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As an AMD user , "In Keller we shall all trust" the dude made such great architectures throughout the last 2+ decades , I believe whatever he is working on the Intel side he will design/redesing it for a huge leap over their current architectures.
 
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Hey Jim, this is 2002 calling, and we want all our outdated, stone-aged cpus back, like, yesterday...

jeez, whatasnoozefest........
 
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