JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of Release 6 of the DDR3 Serial Presence Detect (SPD) document. The updated standard, SPD4_01_02_11: SPD Annex K - Serial Presence Detect (SPD) for DDR3 SDRAM Modules (Release 6), describes new memory timing parameters and enables higher capacity memory modules, and may be downloaded free of charge from the JEDEC website. "The DDR3 memory module market is in its full stride, with new applications pushing the technology into an ever-widening array of offerings, and the Serial Presence Detect is a reliable and consistent way to document the features of these new modules so that system software can tune system performance," said Mian Quddus, Chairman of JEDEC's JC-45 Committee for Dynamic Random Access Memory (DRAM) Modules. He added, "This release of the DDR3 SPD standard adds support for memory modules with up to 8 ranks of DDR3 SDRAMs, enabling 64GB per slot using mainstream 4Gb memory chips." JEDEC's JC-45 Committee for Memory Modules developed the SPD standard in conjunction with the development of the new module types with the objective of enabling performance optimizations based on the characteristics of the DDR3 memories used on each module. SPDs are present on all JEDEC DRAM modules. Parameters such as storage capacity, speed, voltages supported, and the presence of thermal sensors allow systems to configure systems dynamically by reading the SPD on each module at initialization time. Modules using the new parameters in DDR3 SPD document release 6 will be released over the coming year. System software can detect the availability of new information by examining the SPD revision code programmed onto each module.