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NEO Semiconductor X-NAND Standard Offers Performance Comparable to SLC at Costs of QLC, Wins FMS 2020 Best of Show

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NEO Semiconductor was honored with a Flash Memory Summit 2020 Best of Show Award for Hardware Architecture at today's Flash Memory Summit 2020 Best of Show Awards ceremony. The Flash Memory Summit, the World's largest and most prestigious storage industry conference and exposition, recognizes NEO Semiconductor's X-NAND product solution.

"5G, robotics, virtual reality and AI applications demand the highest level of performance in order to meet the service level objectives of business-critical data center workloads," said Jay Kramer, Chairman of the Awards Program and President of Network Storage Advisors Inc. "We are proud to recognize NEO Semiconductor X-NAND product solution for providing an excellent high-performance solution that can uniquely lower the cost across all tiers of SSD technologies."



"We are delighted to receive this award in the world-famous Flash Memory Summit. It is a fantastic honor and achievement for the debut of X-NAND," said Andy Hsu, founder and CEO, NEO Semiconductor. "X-NAND architecture is a monumental breakthrough in NAND flash memory design. From SLC to QLC, each generation's NAND flash capacity has grown larger and costs have become cheaper, but its speed has also become significantly slower. This bottleneck for QLC NAND prevents its use in applications that require high speed performance. Our X-NAND architecture solves this bottleneck by increasing the planes of the array using the existing page buffer size, which increases the parallelism for read and write operations. As a result, X-NAND can achieve QLC density with SLC speed."

According to show organizers, a record number of award submissions were received this year making the judging challenging and each of the categories extremely competitive.

Details of the FMS 2020 award can be found here.

View at TechPowerUp Main Site
 
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This sounds promising. I want to see this technology in action.

My questions are: is this any more reliable than QLC NAND? Will manufacturers forgo QLC and TLC altogether if this proves to be comparable in reliability to TLC? How will this affect product stacks?

Even if the answers are disappointing, I still like to see new flash developments.
 
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Why not normal text but PDF? Maybe there exist peoples which has not wish to download this files.
Sorry, but why are you asking me? I don't work for or represent the company in any way.
 
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Agree. No reason to quote if you in pain for this I'll will edit my comment.
It's not "pain", just a bit confused. I simply provided a data point for those interested.
 

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But what about endurance...

I watched the presentation, have read through it a few times (I have the PDF and a video rip I made hosted on my site), and have written in collaboration about this technology so I can answer any questions about it. Endurance/reliability is improved by writing always in SLC mode and without disturb (see pg. 49).

My questions are: is this any more reliable than QLC NAND? Will manufacturers forgo QLC and TLC altogether if this proves to be comparable in reliability to TLC? How will this affect product stacks?

It's made for the data center, cloud, AI, 5G, that sort of thing. Getting the most out of QLC was a big topic at FMS 2020, usually with a goal to make it equal or superior to TLC for example. In the presentation he shows how it will always write in a SLC-like mode and with the bitline shielding and staggering it does not introduce any additional disturb which normally reduces reliability. Disturb in general is not as big a deal with 3D NAND but regardless the write policy with 3 banks is as such (quote):

"Bank 1 performs SLC programming for input data, Bank 2 performs QLC programming to move data from SLC pages to QLC pages, and Bank 3 (will) erase the old data in SLC pages" - at 8 planes per bank, there's 32 pages of data at 4 SLC pages each plane programmed to Bank 1, Bank 2 reads these to 8 planes of QLC pages. So it's always first programmed and erased in a static SLC-like manner (which has higher endurance than native flash and dynamic SLC, usually 30K P/E) with bitline shielding which would be closer to 1.6K P/E in QLC. He actually doesn't explicitly state endurance - I need to ask him about that - but it would be dependent on workload. My guess would be a goal of TLC-like endurance.
 
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meeh, unless it reads: ....offers performance AND endurance comparable)
i dont care if stuff is "enterprise/data center" or whatever, as long as i can use it (interface) and buy it,
but anything below MLC (maybe TLC for nvme) is a no for me when it comes to OS/game/backup drives.
 
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But what about endurance...
and this is a most important question!
Indeed it is!
Good reads but those data sheets do not answer the above question directly.

It is possible that this new type of NAND is more durable than QLC(the design leans in that direction), but will it be better than TLC and closer to SLC?

Endurance/reliability is improved by writing always in SLC mode and without disturb
But how well? TLC levels? MLC levels? Maybe somewhere inbetween SLC and MLC?
 
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Indeed it is!

Good reads but those data sheets do not answer the above question directly.

It is possible that this new type of NAND is more durable than QLC(the design leans in that direction), but will it be better than TLC and closer to SLC?


But how well? TLC levels? MLC levels? Maybe somewhere inbetween SLC and MLC?
Yes, a lot of unanswered questions, but I doubt we'll get real answers to that until someone actually implements this in a product, which might be some time away.
 
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I watched the presentation, have read through it a few times (I have the PDF and a video rip I made hosted on my site), and have written in collaboration about this technology so I can answer any questions about it. Endurance/reliability is improved by writing always in SLC mode and without disturb (see pg. 49).



It's made for the data center, cloud, AI, 5G, that sort of thing. Getting the most out of QLC was a big topic at FMS 2020, usually with a goal to make it equal or superior to TLC for example. In the presentation he shows how it will always write in a SLC-like mode and with the bitline shielding and staggering it does not introduce any additional disturb which normally reduces reliability. Disturb in general is not as big a deal with 3D NAND but regardless the write policy with 3 banks is as such (quote):

"Bank 1 performs SLC programming for input data, Bank 2 performs QLC programming to move data from SLC pages to QLC pages, and Bank 3 (will) erase the old data in SLC pages" - at 8 planes per bank, there's 32 pages of data at 4 SLC pages each plane programmed to Bank 1, Bank 2 reads these to 8 planes of QLC pages. So it's always first programmed and erased in a static SLC-like manner (which has higher endurance than native flash and dynamic SLC, usually 30K P/E) with bitline shielding which would be closer to 1.6K P/E in QLC. He actually doesn't explicitly state endurance - I need to ask him about that - but it would be dependent on workload. My guess would be a goal of TLC-like endurance.

Thank you so much for this information. You certainly live up to your SSD Guru title.
 

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Why not normal text but PDF? Maybe there exist peoples which has not wish to download this files.
Could it have something to do with this not being a bedtime story and having a crapload of diagrams in there?
I know, ASCII art is cool, but not everyone has mastered that.
 
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Could it have something to do with this not being a bedtime story and having a crapload of diagrams in there?
I know, ASCII art is cool, but not everyone has mastered that.

You got your bedtime stories in ASCII art? :eek:

Man my youth sucked
 
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