Ya I've been busy too man. But here's some stuff to hopefully help out:
DDR2 Section: 1) Mention somewhere in this article that DDR & GDDR are totally different and are 100% uncorrelated to each other.
2)
Here's a more indepth explanation of memory timings I found, in case you want to use it or pull from it:
"
CAS:
CAS is Column Address Strobe or Column Address Select. CAS controls the amount of time (in cycles (2, 2.5,& 3) between receiving a command and acting on that command. Since CAS primarily controls the location of HEX addresses, or memory columns, within the memory matrix, this is the most important timing to set as low as your system will stably accept it. There are both rows and columns inside a memory matrix. When the request is first electronically set on the memory pins, the first triggered response is tRAS (Active to Precharge Delay). Data requested electronically is precharge, and the memory actually going to initiate RAS is activation. Once tRAS is active, RAS, or Row Address Strobe begins to find one half of the address for the required data. Once the row is located, tRCD is initiated, cycles out, and then the exact HEX location of the data required is accessed via CAS. The time between CAS start and CAS end is the CAS latency. Since CAS is the last stage in actually finding the proper data, it's the most important step of memory timing.
tRCD:
Also known as RAS to CAS Delay, in addition to Column Address Strobe, there is Row Address Strobe. CAS and RAS combined allow for the exact location of memory blocks. There is an interval between RAS (activated when data is first requested) and CAS (activated when RAS is complete), as memory can't locate a block precisely in a single stage. tRCD is the cycle time between the first stage in memory access, the row strobe, and the second stage. However, the performance impact of this setting is often neglible, as memory tries to store data from programs in sequential order. It tries to keep the same row for a single program, and ordered columns to reduce the time for tRCD.
tRP:
Also known as RAS Precharge, this is the amount of time it takes for memory to terminate the access in one row and begin another. To put it simply, after data is set to the pins and activates tRAS, then RAS, tRCD, and CAS; the memory needs to terminate its current row and start all over at tRAS. This is the very basic function of how memory works. This is only an important setting when you're doing massive shifting in data, for example - working with large virtual buffers or video rendering. At that point, several rows are being consumed by a single program, and its advantageous for the program to be able to switch quickly between these rows.
tRAS:
Also known as Active to Precharge Delay, this is the time between receiving a request for data electronically on the pins of a memory module and then initiating RAS to start the actual retrieval of data. This command seems important, but really it isn't. Memory access is a very dynamic thing. Sometimes memory is being hit hard, and other times very sporadically. Though at all times, memory access is at constant, therefore, it is rare that the tRAS command is received to access new data (such as a substantial change, like opening a new program). "
This is obviously a little more in depth, maybe too much for "Basics," but whatever you can pull is good. The current explanation you put up for the tRP is a little confusing.
Or just use the techPowerUp! explanation:
http://www.techpowerup.com/articles/overclocking/AMD/memory/131
