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Rambus Aims for Terabyte-Per-Second Memory Bandwidth

Discussion in 'News' started by malware, Nov 26, 2007.

  1. malware New Member

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    Rambus Inc. plans to announce this Wednesday a new memory signaling technology initiative targeted at delivering a Terabyte-per-second of memory bandwidth, which the company touts as a solution for next-generation multi-core, game and graphics applications. Rather than simply increasing the clock speed of memory to achieve higher output, Rambus looks to boost bandwidth with a 32X data rate. Just as DDR memory technologies doubles transfer on a single, full clock signal cycle, Rambus’ proposed technology is able to data at 32 times the reference clock frequency. With 32X technology, the memory company is targeting a bandwidth of 16Gbps per DQ link with memory running at 500MHz. In contrast, today’s DDR3 at 500MHz achieves a bandwidth of 1Gbps. The terabyte bandwidth memory method is slated for year 2011. Rambus has also recently received early silicon capable of demonstrating its technology. The early test rig uses emulated DRAM chips, connected to a Rambus memory controller at a 32X data rate capable of 64Gbps. Rambus will show it this Wednesday at the Rambus Developer Forum in Tokyo, Japan.

    Source: DailyTech
     
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  2. kwchang007

    kwchang007 New Member

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    Holy shiz....a 32x multipler in essence on ram. That'd be so amazing. But what kind of energy consumption/heat/price/new mobos are we looking at here?

    I think Rambus may have something here.
     
    Last edited: Nov 26, 2007
  3. Morgoth

    Morgoth

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    thats realy F8cking aswome
     
  4. beesagtig

    beesagtig New Member

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    Cant wait for that!!

    P.S oops necro post:(
     
  5. DanTheBanjoman Señor Moderator

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    Great, do we have anything that uses XDR2 yet?

    Quite interesting to see how this turned out to be nothing :)
     
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