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Ryzen 3000 - 2 questions

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1. If I purchase Ryzen 3600/3600X CPU (in July), paired up with a B450/X470 motherboard (giving the X570 a miss), would this combination work straight out of the box?
That will depend on the board and if the maker updated the BIOS with the proper micro-code, which most are and have been for a few months as the micro-code has been final for that long.
Or would I need a previous generation AMD ryzen chip to update the BIOS first?
As long as you buy a board that states it's Ryzen 3xxx ready( and every retailer will be highlighting this to drive sales), you'll have no issues.
2. Does the larger cache size matter with these newer 3000 Ryzen CPUs? One of AMDs charts was calling this "game cache" for which I'm assuming helps gaming in one way or another?
Yes, the vast majority of games will easily benefit more from a greater amount of L1/L2/L3 cache than from a greater number of cores. Bang-for-buck, if money is tight, the Ryzen 3600 is the best value balance between price/performance. If you have more money to spend, then the 3800X gives the best performance in games due to the higher clock speeds. Reference the chart below.
LaunchRyzen3xxxModelChart.jpg

[Above chart thanks to TPU found here; https://www.techpowerup.com/256425/amd-ryzen-3-3200g-and-ryzen-5-3400g-detailed-new-slide-leak]
 
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The cache is usually to keep the data in the buffer, first in first out...
Ummm, sorry but no! It is not first in and first out (FIFO). Something can be first in then sit in there for hours if it is high priority and needs to be frequently accessed. In the mean time, other data can come in, sit awhile and then be dumped. At the same time, even other data can come in then go right back out. It all depends on the data's priority and how often it is needed. If the data is determined to be of low priority, it can be last in and first out.

The algorithms to manage that data most efficiently are pretty sophisticated - much more complex than managing FIFO data. The goal is to ensure the next bit of data the CPU needs is already loaded into the fastest cache. Whether that was just loaded or not is immaterial. The workload does not matter either. That implies if the user is just goofing off and paying solitaire, then the caches are not used. Not so.

It is all about the priority of the data the CPU needs next. It has nothing to do with FIFO.
 
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Ummm, sorry but no! It is not first in and first out (FIFO). Something can be first in then sit in there for hours if it is high priority and needs to be frequently accessed. In the mean time, other data can come in, sit awhile and then be dumped. At the same time, even other data can come in then go right back out. It all depends on the data's priority and how often it is needed. If the data is determined to be of low priority, it can be last in and first out.

The algorithms to manage that data most efficiently are pretty sophisticated - much more complex than managing FIFO data. The goal is to ensure the next bit of data the CPU needs is already loaded into the fastest cache. Whether that was just loaded or not is immaterial. The workload does not matter either. That implies if the user is just goofing off and paying solitaire, then the caches are not used. Not so.

It is all about the priority of the data the CPU needs next. It has nothing to do with FIFO.
To clarify my post, the cpu uses fifo most of the time, yes some data can sit there for hours and hours.
 
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To clarify my post, the cpu uses fifo most of the time
??? "Most" of the time? No it doesn't. :(

It "fetches" the next instruction based on what it needs next - and that can be based on a whole host of variables from user input, program input, network status, hardware drivers, interrupts and so on.

Whether that next instruction is next in line or not (in terms of FIFO) is irrelevant. If the next instruction was loaded next, then fine. But if not, the CPU will look in the next L cache or go out to RAM or to the disk to get the next chunk of data it "needs".

FIFO is often used - no denying that. Getting and sending data to the modem, for example, is typically FIFO. But inside the CPU "most" of the time, no! The CPU is fetching data from all sorts of I/Os as it needs it.
 
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Will the better memory support of Ryzen 3000 be available on previous chipsets (x470 and b450)? Or will you have to buy the 500-series chipsets to take advantage of newer and better memory support?
 
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Will the better memory support of Ryzen 3000 be available on previous chipsets (x470 and b450)? Or will you have to buy the 500-series chipsets to take advantage of newer and better memory support?
Considering that the memory controller is inside the CPU package (part of the I/O chiplet), I would think you'd only need a new CPU. That said, the board layout between the socket and memory slots would also have something to do with it.
 
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Will the better memory support of Ryzen 3000 be available on previous chipsets (x470 and b450)? Or will you have to buy the 500-series chipsets to take advantage of newer and better memory support?
A comprehensive review of the 3000s and the new chip-set is not a 20 page thing. So many good questions.
 
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You posed a good question. There are many others like would a lower end B350 MB handle a 3950x to more than stock. How would stock clocks be compared to if you put that same CPU in a good x570 board and so on.
 
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Oh, I thought you were telling me to go read that 20 pages of whatever.
 
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Oh, I thought you were telling me to go read that 20 pages of whatever.
I think not should have been now in his post. I am really only concerned with XFR/PBO. If all new functions (if there are) of XFR/PBO in Zen 2 are supported in X470/B450, then I am buying a 400 series. I don't need pcie4.
 
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