Ryzen 3000, FCLK Issue

[Zach_01]

Did not have well over an hour to look, but on first glance, this information has only to do with AIDA64 correct? Bandwidth and latency?

Mainly but not just it...

Those vids and especially the first one...

...can help anyone understand what short of settings can one make with DRAM(MEMCLK), UnifiedMemController(UCLK), InfinityFabric(FCLK) speeds.
InfinityFabric can work independedly and decoupled from the other 2.
DRAM and UMC can work either in 1:1 or 2:1 ratio.

So you have 3 subsystems
MEMCLK (memory)
UCLK (controller)
FCLK (IF)

The best scenario is to work all 3 of them in 1:1:1 ratio. Unfortunately this works only up to 1900MHz. (DRAM=3800MT/s=MEMCLK=1900MHz, UCLK=1900MHz, FCLK=1900MHz). Not all boards and CPUs can do that tho.

Then if you have real high speed memory, like 4400MT/s (2200MHz real speed) and want to run it up there, then best you can do is to run:

FCLK = decoupled and highest possible (1833, 1866, 1900)
passing 1900MHz real DRAM speed (MEMCLK) will auto adjust UCLK to 2:1 ratio.
So if you ran MEMCLK = 2200MHz (4400MT/s) the UCLK will run = 1100MHz and thats it. Thats the best you can do.

See below an example of DRAM to 4000MT/s (MEMCLK=2000MHz), UCLK(2:1mode)=1000MHz, and IF(FCLK)=1900MHz
Mind not the timings, this only to demostrate speeds:

Here is another one with 4200MT/s (MEMCLK=2100MHz), UCLK=1050MHz), IF(FCLK=1900MHz)

---------------------------------------------------------------------------

All these subsystems have their own voltages that can be adjusted for attempting stability in high speeds.

Everybody knows the DRAM voltage, nothing to say here...

UCLK and IF voltages are derived from SoC voltage, otherwise the I/O chiplet voltage.
So UCLK and IF voltages cannot be above or equal to SoC voltage. Only lower.

By default
CPU SoC voltage on 3000 is 1.05~1.08V
UCLK voltage (cLDO VDDP) and InfinityFabric voltage (cLDO VDDG) is well below 1.0V.
IF voltage, cLDO VDDG in some boards and after latest 1.0.0.4B AGESA is devided into 2 sections.
1. cLDO VDDG IOD (is the Infinity Fabric voltage for the I/O Die or SoC IF part)
2. cLDO VDDG CCD (is the Infinity Fabric voltage for the cores IF part, inbetween the CCX/CCDs connection)
These can be found in "AMD CBS" section of UEFI and under "XFR Enhancement", or in "AMD Overclocking" section and under SOC, VDDP/VDDG voltage.

SoC has a safe voltage level up ot 1.25V (although past 1.15V I doubt anyone will see any benefit)
cLDO VDDP/VDDG must be at least 50mV below SoC voltage, (although past 1.05V I doubt anyone can see any benefit)

Keep in mind that raising SoC, and cLDOs voltages and speeds (UCLK/FCLK) will increase power consumption of I/O Die by a few Watts that you will lose from overall CPU package power draw (PPT) when CPU is auto boosting and with stock PBO settings. You may also see some cores (middle/low speed ones) loose about 25MHz of single or low thread boost. All core boosting will be affected also, but not so much of the actual highest speed, but for the sustainability of it.

 

[Voltaj .45 ACP]

You should see all 4 videos, the whole thing of each and then understand what is the memory subsystem nature of Ryzen 3000. By watching a glimpse of 1 video, and listen only a few words of it, and draw conlusions or anything else is not the optimal way. There is a specific reason I posted those videos. If you dont want to listen to them as info, its ok by me.


False...
The 1:1 ratio is kept up to 3800MT/s DRAM and 1900MHz UCLK:FCLK

View attachment 145534

that's what i've talked about! 3733/1866 cl16 better than anything.no tweaking not cpu oc.this cpus can't handle above 1866 because of that i've said i'm waiting 4000 series.

 

[Zach_01]

View attachment 145595

that's what i've talked about! 3733/1866 cl16 better than anything.no tweaking not cpu oc.this cpus can't handle above 1866 because of that i've said i'm waiting 4000 series.

And it’s sure it won’t do 1900MHz?
How is your voltages?
A RyzenMaster screenshot will do...

 

[tabascosauz]

Did not have well over an hour to look, but on first glance, this information has only to do with AIDA64 correct? Bandwidth and latency?

1:1:1 UCLK:FCLK:MCLK like most people run makes things easy - I don't think we're all on the same page here. From what I can tell, you are indeed correct; FCLK (IF) can be whatever you want it to be, within reason, which is the point of the Matisse's dividers no longer requiring the three to be hand-in-hand. UCLK (mem controller) doesn't appear to be so flexible. If the three are synced, then UCLK=FCLK=MCLK, but at anything other than 1:1, UCLK is stuck in a 1:2 relationship with MCLK, and cannot be whatever you want it to be, unlike FCLK. When not at 1:1:1, there is no rule that the memory controller must be synced with IF.

Hence what I was saying, in one of BZ's videos (as well as another review elsewhere entailing kits from 2400 to 4200MT/s, GN I think), that if you find the "perfect" unsynced FCLK clock such as 1800 for 3200MT/s or 1900 for 4200MT/s, then running unsynced isn't all so end-of-the-world doom and gloom as people make it out to be.

But at the end of the day, very few people try it because performance differs noticeably even from board to board, so documentation is scarce. That, and the few reviews that exist don't seem to agree on what kind of RAM speed you actually need to overcome that inherent ~8ns handicap of 1:2, because testing is far from standardized. And I mean, tight 3733 1:1 and 3800 1:1 also exist, so...

The gamersnexus test I mentioned with all the different kits had 3800/16 1:1 and 4200/16 FCLK 1900 at the top of the list in pretty much all the tests, but 4200 barely edged out 3800 1:1 in just one instance, I think. Since both of those leading presets require 1900 IF, which we know OP can't do on this chip, it sounds like there's not too much point in pushing past 3733.

 

[Zach_01]

If you can’t run 1900MHz 1:1:1 then 1866 is the next best thing.
And if you can do it with lowest possible timings, the better. tRFC is also a significant setting.

So past 1900MHz (3800) you will need 5000+ DRAM kit in order to be able to work UCLK high enough to compensate for the 2:1 ratio.

Threadripper, with quad channel is a different story...

 

[Voltaj .45 ACP]

And it’s sure it won’t do 1900MHz?
How is your voltages?
A RyzenMaster screenshot will do...

yeah it will be 1900 mhz fclk but i have to voltage 1.1 on some vdd setting about IF and it's lower scores than 1866.maybe pushed with voltage don't gave best results because uclk being 1:2 and you know the rest.

ac odyssey 2k very high.bottom left to right: uclk, cpu fans, case fan, x570 chipset and rams.about 40 min.3733/1866 cl16 1.4v but now i'm trying 1.39v

 

[sneekypeet]

I see a lot trying to educate me on the relationships. Not so much my point. You all say 1 to 1 to 1 gets me the best latency in aida64, which is possible and likely. My point is, in my testing, across my 27 recorded scores in my records for all kits I test, that I see better bandwidth and bench results when they are not linked sometimes. Not always the rule, but imho the best results in aida64 do not translate across the board at all times.

I guess my issue is I am too old school. I try everything first, then make a decision.

 

[Zach_01]

yeah it will be 1900 mhz fclk but i have to voltage 1.1 on some vdd setting about IF and it's lower scores than 1866.maybe pushed with voltage don't gave best results because uclk being 1:2 and you know the rest.

ac odyssey 2k very high.bottom left to right: uclk, cpu fans, case fan, x570 chipset and rams.about 40 min.3733/1866 cl16 1.4v but now i'm trying 1.39v

Look again post #24. You can run all of them on 1900MHz. You just have to set in UEFI the
MEMCLK==UCLK, while you have set FCLK to 1900MHz, and memory multi to x38.
Look around in you BIOS and you will find it the MEMCLK==UCLK.
And clearly you are not familiar with voltages in there as you don’t even know what you changing and what for...

You should know what is what. I’m going to repeat my previous writings and if you want to understand what you can do to improve stability pay attention to every sentence.

“UCLK and IF voltages are derived from SoC voltage, otherwise the I/O chiplet voltage.
So UCLK and IF voltages cannot be above or equal to SoC voltage. Only lower.

By default
CPU SoC voltage on 3000 is 1.05~1.08V
UCLK voltage (cLDO VDDP) and InfinityFabric voltage (cLDO VDDG) is well below 1.0V.
IF voltage, cLDO VDDG in some boards and after latest 1.0.0.4B AGESA is devided into 2 sections.
1. cLDO VDDG IOD (is the Infinity Fabric voltage for the I/O Die or SoC IF part)
2. cLDO VDDG CCD (is the Infinity Fabric voltage for the cores IF part, inbetween the CCX/CCDs connection)
These can be found in "AMD CBS" section of UEFI and under "XFR Enhancement", or in "AMD Overclocking" section and under SOC, VDDP/VDDG voltage.

SoC has a safe voltage level up ot 1.25V (although past 1.15V I doubt anyone will see any benefit)
cLDO VDDP/VDDG must be at least 50mV below SoC voltage, (although past 1.05V I doubt anyone can see any benefit)”

So before you raise cLDO VDDP(UCLK) or cLDO VDDG(IF) to 1.1V you should first raise SoC voltage to 1.15V at least. Otherwise it is pointless to just raise VDDG or VDDP (cLDO). And after you do raise SoC to any voltage you should confirm it in windows with RyzenMaster or HWiNFO64 that has actually raised to what you want, before you touch any voltage of UCLK or IF. Because most boards need SoC voltage LLC to keep it where you want.

What short of ICs you Ram has? If they are Samsung B-die there is no problem running them on 1.45V or even 1.5V with a good amount of air upon them.

I see a lot trying to educate me on the relationships. Not so much my point. You all say 1 to 1 to 1 gets me the best latency in aida64, which is possible and likely. My point is, in my testing, across my 27 recorded scores in my records for all kits I test, that I see better bandwidth and bench results when they are not linked sometimes. Not always the rule, but imho the best results in aida64 do not translate across the board at all times.

I guess my issue is I am too old school. I try everything first, then make a decision.

Please don’t go there... nobody said you have any issue.
While I personally said and meant that 1:1:1 is the ideal and it would be nice to keep that all the way up to 2200MHz if not more, we all know that you can’t, and I also said what someone can do to if likes/wants to run DRAM 4400. And show it...
Of course I didn’t bench when FCLK is decoupled from the other 2, while having them on 2:1 ratio.
The only thing I run when I showcase above the 4200 DRAM speed and the 2100:1050:1900 (MEMCLK:UCLK:FCLK) was the AIDA64 benchmark and the bandwidth was lower (2-3GB/s) and latency +10ns from what I get with 1866:1866:1866.
I wish I had way better Ram to be able to run something like (4400) 2200:1100:1900 (MEMCLK:UCLK:FCLK) with decent timings.

If any body can demonstrate for all to see with different types of benchmarking like AIDA, gaming, editing or rendering, the:

1866:1866:1866 vs 2200:1100:1900
or
1900:1900:1900 vs 2200:1100:1900

...I’m really interested to see something like that.

 

[sneekypeet]

Look again post #24. You can run all of them on 1900MHz. You just have to set in UEFI the
MEMCLK==UCLK, while you have set FCLK to 1900MHz, and memory multi to x38.
Look around in you BIOS and you will find it the MEMCLK==UCLK.
And clearly you are not familiar with voltages in there as you don’t even know what you changing and what for...

You should know what is what. I’m going to repeat my previous writings and if you want to understand what you can do to improve stability pay attention to every sentence.

“UCLK and IF voltages are derived from SoC voltage, otherwise the I/O chiplet voltage.
So UCLK and IF voltages cannot be above or equal to SoC voltage. Only lower.

By default
CPU SoC voltage on 3000 is 1.05~1.08V
UCLK voltage (cLDO VDDP) and InfinityFabric voltage (cLDO VDDG) is well below 1.0V.
IF voltage, cLDO VDDG in some boards and after latest 1.0.0.4B AGESA is devided into 2 sections.
1. cLDO VDDG IOD (is the Infinity Fabric voltage for the I/O Die or SoC IF part)
2. cLDO VDDG CCD (is the Infinity Fabric voltage for the cores IF part, inbetween the CCX/CCDs connection)
These can be found in "AMD CBS" section of UEFI and under "XFR Enhancement", or in "AMD Overclocking" section and under SOC, VDDP/VDDG voltage.

SoC has a safe voltage level up ot 1.25V (although past 1.15V I doubt anyone will see any benefit)
cLDO VDDP/VDDG must be at least 50mV below SoC voltage, (although past 1.05V I doubt anyone can see any benefit)”

So before you raise cLDO VDDP(UCLK) or cLDO VDDG(IF) to 1.1V you should first raise SoC voltage to 1.15V at least. Otherwise it is pointless to just raise VDDG or VDDP (cLDO). And after you do raise SoC to any voltage you should confirm it in windows with RyzenMaster or HWiNFO64 that has actually raised to what you want, before you touch any voltage of UCLK or IF. Because most boards need SoC voltage LLC to keep it where you want.

What short of ICs you Ram has? If they are Samsung B-die there is no problem running them on 1.45V or even 1.5V with a good amount of air upon them.

Please don’t go there... nobody said you have any issue.
While I personally said and meant that 1:1:1 is the ideal and it would be nice to keep that all the way up to 2200MHz if not more, we all know that you can’t, and I also said what someone can do to if likes/wants to run DRAM 4400. And show it...
Of course I didn’t bench when FCLK is decoupled from the other 2, while having them on 2:1 ratio.
The only thing I run when I showcase above the 4200 DRAM speed and the 2100:1050:1900 (MEMCLK:UCLK:FCLK) was the AIDA64 benchmark and the bandwidth was lower (2-3GB/s) and latency +10ns from what I get with 1866:1866:1866.
I wish I had way better Ram to be able to run something like (4400) 2200:1100:1900 (MEMCLK:UCLK:FCLK) with decent timings.

If any body can demonstrate for all to see with different types of benchmarking like AIDA, gaming, editing or rendering, the:

1866:1866:1866 vs 2200:1100:1900
or
1900:1900:1900 vs 2200:1100:1900

...I’m really interested to see something like that.

All i have currently is an Xcel spread sheet of my AMD testing. Not the easiest to share

As to the last bits, try it. Maybe not at those specific numbers, but my point is play around, you might be surprised.

 

[Zach_01]

All i have currently is an Xcel spread sheet of my AMD testing. Not the easiest to share

Plain numbers with every setting on each result will do for me personally. Dont really need visual/screenshot proof if thats the case.

 

[Lindatje]

You cannot set IF higher then your DRAM clock.

for 3200MHz DRAM set the IF on 1600 or lower, for 3600MHz the IF is 1800 ect.

 

[sneekypeet]

Plain numbers with every setting on each result will do for me personally. Dont really need visual/screenshot proof if thats the case.

I'm not trying to avoid the challenge, just at this exact point in time, I cannot run benches and change things, I'm tied up in work related things.
If I remember this at the beginning of the month, we can take this to PMs and pick some sticks to test, use both of our heads together, and we can post results of it in this thread then.

@Lindatje maybe with your motherboard that is a thing, but all sticks I have tested on AMD will run with 1800 IF. Let me see if I can get an image to explain what I mean.

3200MHz memory 1800 IF.

 

[Zach_01]

Sure why not...
And it’s not going to be a challenge in between opinions. I’m always looking for this kind of education.

I’m too in the middle of something right now regarding PBO settings and testing and it will take me several days to finish, wanting to do a review kind of thread/topic.

You cannot set IF higher then your DRAM clock.

for 3200MHz DRAM set the IF on 1600 or lower, for 3600MHz the IF is 1800 ect.

Of course you can... You can decouple FCLK from DRAM and run it whatever you like, lower or higher. It’s the Memory and the Controller that you can’t run differently other than 1:1 or 2:1 depending the speed.

 

[Voltaj .45 ACP]

Look again post #24. You can run all of them on 1900MHz. You just have to set in UEFI the
MEMCLK==UCLK, while you have set FCLK to 1900MHz, and memory multi to x38.
Look around in you BIOS and you will find it the MEMCLK==UCLK.
And clearly you are not familiar with voltages in there as you don’t even know what you changing and what for...

You should know what is what. I’m going to repeat my previous writings and if you want to understand what you can do to improve stability pay attention to every sentence.

“UCLK and IF voltages are derived from SoC voltage, otherwise the I/O chiplet voltage.
So UCLK and IF voltages cannot be above or equal to SoC voltage. Only lower.

By default
CPU SoC voltage on 3000 is 1.05~1.08V
UCLK voltage (cLDO VDDP) and InfinityFabric voltage (cLDO VDDG) is well below 1.0V.
IF voltage, cLDO VDDG in some boards and after latest 1.0.0.4B AGESA is devided into 2 sections.
1. cLDO VDDG IOD (is the Infinity Fabric voltage for the I/O Die or SoC IF part)
2. cLDO VDDG CCD (is the Infinity Fabric voltage for the cores IF part, inbetween the CCX/CCDs connection)
These can be found in "AMD CBS" section of UEFI and under "XFR Enhancement", or in "AMD Overclocking" section and under SOC, VDDP/VDDG voltage.

SoC has a safe voltage level up ot 1.25V (although past 1.15V I doubt anyone will see any benefit)
cLDO VDDP/VDDG must be at least 50mV below SoC voltage, (although past 1.05V I doubt anyone can see any benefit)”

So before you raise cLDO VDDP(UCLK) or cLDO VDDG(IF) to 1.1V you should first raise SoC voltage to 1.15V at least. Otherwise it is pointless to just raise VDDG or VDDP (cLDO). And after you do raise SoC to any voltage you should confirm it in windows with RyzenMaster or HWiNFO64 that has actually raised to what you want, before you touch any voltage of UCLK or IF. Because most boards need SoC voltage LLC to keep it where you want.

What short of ICs you Ram has? If they are Samsung B-die there is no problem running them on 1.45V or even 1.5V with a good amount of air upon them.

Please don’t go there... nobody said you have any issue.
While I personally said and meant that 1:1:1 is the ideal and it would be nice to keep that all the way up to 2200MHz if not more, we all know that you can’t, and I also said what someone can do to if likes/wants to run DRAM 4400. And show it...
Of course I didn’t bench when FCLK is decoupled from the other 2, while having them on 2:1 ratio.
The only thing I run when I showcase above the 4200 DRAM speed and the 2100:1050:1900 (MEMCLK:UCLK:FCLK) was the AIDA64 benchmark and the bandwidth was lower (2-3GB/s) and latency +10ns from what I get with 1866:1866:1866.
I wish I had way better Ram to be able to run something like (4400) 2200:1100:1900 (MEMCLK:UCLK:FCLK) with decent timings.

If any body can demonstrate for all to see with different types of benchmarking like AIDA, gaming, editing or rendering, the:

1866:1866:1866 vs 2200:1100:1900
or
1900:1900:1900 vs 2200:1100:1900

...I’m really interested to see something like that.

hehe trust me i've voltage everywhere but not in amd overclocking.. maybe i'm looking wrong place.will try ASAP thank you.

 

[Zach_01]

View attachment 145825

hehe trust me i've voltage everywhere but not in amd overclocking.. maybe i'm looking wrong place.will try ASAP thank you.

View attachment 145826

Its B-die then...
If I had your CPU and DRAM, now that I know some stuff about 3000 I would start by disabling XMP
run DRAM multi X38, manual CL16-16-16-16-32-48, tRFC: 358, tRFC2: 266, tRFC4: 164 (all else t auto) DRAM voltage 1.45V
FCLK 1900MHz, MEMCLK==UCLK
CPU SoC voltage auto, with CPU SoC LLC one level before max.
cLDO VDDG: 1025mV
cLDO VDDP: 1000mV

 

[Voltaj .45 ACP]

i think my bios is a little different.i've found this setting in amd oc and interesting.this was disabled but setting enabled not change a bit.

and this is not feel right to me:

1050 what's that?what kind of voltage is this?i didn't set but i've tried 1.15 soc and you can see in the second picture.maybe my cpu is not quality enough.i've been overclocking since 1996 and if this is hard like this then it not gonna happen because i have force i didn't have to second try in oc most of the time but this time i gave up.i need 4000 series stupid IO thing.thank you for your help i appreciated.

 

[Zach_01]

Last screenshot "VDDP Voltage Control" is not for UCLK. its something else DRAM related. Leave it auto.

"CLDO VDDP voltage" is for UCLK and the 1050 is in mV (miliVolts) 1050mV = 1.05V

EDIT:
I forget to mention the 99.8MHz BCLK can be an equal 100 if you find and disable spread spectrum

 

[Voltaj .45 ACP]

Last screenshot "VDDP Voltage Control" is not for UCLK. its something else DRAM related. Leave it auto.

"CLDO VDDP voltage" is for UCLK and the 1050 is in mV (miliVolts) 1050mV = 1.05V

EDIT:
I forget to mention the 99.8MHz BCLK can be an equal 100 if you find and disable spread spectrum

from reddit

ckurobac

AMD 3700X+Vega6412 points·5 months ago

No spread spectrum settings on my X570 Strix-E，so I paid $300 for a low end motherboard，good job asus


https://www.reddit.com/r/Amd/comments/czbai7
idk what's for but you asked for it:

 

[Zach_01]

Strix X570-E is no low end board. Just Asus messed up somethings with some boards, me thinks...
Also your board does not report VRM temps because they say that they couldn’t make the algorithm work properly and report an accurate value, so they block it. It’s a shame, although your board has quiet enough VRM pwr and efficiency that can handle 3950X without VRM cooling.
Asus have more X570 boards than any other vendor with strange feature combinations, making some boards (through the entire X570 line) irrelevant. Sorry to say, but your board is one of them.

The more time goes by, the more I think the Aorus X570 line may be the best overall.
The AorusPro X570 I have is a 230$ board right now and has things that Strix-E does not. The only thing missing is the debug code display, but I prefer not having it instead other.

from reddit

ckurobac

AMD 3700X+Vega6412 points·5 months ago

No spread spectrum settings on my X570 Strix-E，so I paid $300 for a low end motherboard，good job asus


https://www.reddit.com/r/Amd/comments/czbai7
idk what's for but you asked for it:

View attachment 145920

Why 1.363V for SoC voltage? That is too much and could degrade I/O die in the long term.
Didn’t you try 1900:1900:1900?

 

[Voltaj .45 ACP]

Strix X570-E is no low end board. Just Asus messed up somethings with some boards, me thinks...
Also your board does not report VRM temps because they say that they couldn’t make the algorithm work properly and report an accurate value, so they block it. It’s a shame, although your board has quiet enough VRM pwr and efficiency that can handle 3950X without VRM cooling.
Asus have more X570 boards than any other vendor with strange feature combinations, making some boards (through the entire X570 line) irrelevant. Sorry to say, but your board is one of them.

The more time goes by, the more I think the Aorus X570 line may be the best overall.
The AorusPro X570 I have is a 230$ board right now and has things that Strix-E does not. The only thing missing is the debug code display, but I prefer not having it instead other.


Why 1.363V for SoC voltage? That is too much and could degrade I/O die in the long term.
Didn’t you try 1900:1900:1900?

of course not low end but they wanna be spoiled top model(formula?) users in somehow.stupid asus.

no oc no tweak no cheat.stock+pbo enabled

 

[oxrufiioxo]

of course not low end but they wanna be spoiled top model(formula?) users in somehow.stupid asus.

no oc no tweak no cheat.stock+pbo enabled

The Strix E is a pretty good board its just priced stupidly at its normal 330 price its way too close to the Hero. If priced at 300 usd or less it's a pretty good option and I would probably opt for it over the other similar priced boards if that were the case.

in your ryzen master screenshot your SOC Voltage seems stupidly high it should be 1.2v or less afaik.

 

[Zach_01]

in your ryzen master screenshot your SOC Voltage seems stupidly high it should be 1.2v or less afaik.

Yes yes, thanks for mention it too... I already did but seems that it got bypassed.

It should be 1.05~1.08V when stock and 1.1~1.15V when DRAM/UC/IF OC. More than this its just making SoC power hungry and could stealing boost headroom from Cores (PPT). And of course could degrade SoC rather quickly...

 

[oxrufiioxo]

Yes yes, thanks for mention it too... I already did but seems that it got bypassed.

It should be 1.05~1.08V when stock and 1.1~1.15V when DRAM/UC/IF OC. More than this its just making SoC power hungry and stealing boost headroom from Cores (PPT). And of course could degrade SOC rather quickly...

That's the only thing I hate about Asus boards they run the memory voltages way too high even on Intel systems..... Makes no sense to me. Also they can be priced shitty but they sure do look good typically

 

[pcwolf]

This is a bookmark I am the noob completely swamped trying to keep up.
You folks are so conversant, flinging acronyms and synonyms and aliases around, no doubt in my mind you can sling a pork chop past a starving dog.

SO ...

I can set fCLK and uCLK directly with UEFI options (mostly by setting fCLK and then coupling)

BUT ...

There is NO direct setting of the mCLK available
I must set it INDIRECTLY with "MEMCLK==UCLK" in UEFI

Have I got that right?

I will deal with voltages later, after I got this timing relationship in my head.

 

[Zach_01]

This is a bookmark I am the noob completely swamped trying to keep up.
You folks are so conversant, flinging acronyms and synonyms and aliases around, no doubt in my mind you can sling a pork chop past a starving dog.

SO ...

I can set fCLK and uCLK directly with UEFI options (mostly by setting fCLK and then coupling)

BUT ...

There is NO direct setting of the mCLK available
I must set it INDIRECTLY with "MEMCLK==UCLK" in UEFI

Have I got that right?

I will deal with voltages later, after I got this timing relationship in my head.

First must know what is all those sub-parts of the Ryzen 3000 CPU
These CPUs have a unique layout that separates them from every other CPU out there. Today's (all)CPUs are called also a SoC (system on chip) or a part of them, especially the smartphones CPUs. Because its not all computation cores. They have integrated memory controller. They have direct links with PCI-E slots, m.2 NVMe/SATA drives, USB ports... and other subsystems that once (15~20y ago) was integrated strictly to board chipsets (north/south bridge). A lot of them today exist on the CPU die it self making comm with CPU cores faster.
These parts of CPU called I/O (input/Output) or SoC.

Ryzen 2000

The cores inside CCXs comm with the rest of the chip (I/O) with InfinityFabric.

AMD, on Ryzen 3000 took all those subsystems and placed them on a separate die and now we have dies (or chiplets) with cores only (CCX0+1 = CCD) and an I/O Die placed in the same package.

This is the 8core chiplet containing 2xCCX (CoreCompleX) forming a CCD (CoreComplexDie)


This is the I/O die or SoC

https://forum.level1techs.com/uploads/default/original/3X/0/5/05587a80460d444d59dc7d0a41507b3f9905b03f.jpeg

This is the layout of the entire system


And this is the CPU package


The above is your CPU containing 2x8core chiplets(CCDs) and the I/O. The I/O (SoC) die contains the UMC (Unified Memory Controller) and its speed called UCLK. The Infinity Fabric is in between I/O and core dies that connects all together and its speed called FCLK.
DDR4 on AM4 is linked to the IO die with 2 separate channels (hence the dual channel function). Each channel is 64bit width. The true speed of RAM is called MEMCLK. When you say DDR4 3600 the 3600 is the effective speed (3600MegaTransfers/s). The true speed of RAM is 1800MHz and we call it 3600 because we have 2 data transfers in every tic (hence DDR=Double Data Rate).
So when you set you DRAM multi to X38 (DDR3800) the MEMCLK is 1900MHz. Set this: MEMCLK==UCLK and you are syncing the RAM with the memory controller. Set FCLK also at 1900MHz and all three parts from RAM to CPU cores are synced and theoretically are maximizing performance. Different/uneven speeds could mean potential stall of data, lower memory bandwidth, and high latency.

DRAM(MEMCLK) --> UMC(UCLK) --> IF(FCLK) --> Cores
--------1900 -----------> 1900 -------> 1900 ---> CoreSpeed (3200~4700MHz)

Unfortunately the UMC and IF are the big bottlenecks in the line of Data transfer to Cores. Depending on the CPU mostly and the board the UMC and the IF can run maxed out from 1733MHz to 1900MHz.
Up until 1900 can all three parts work on the same speed. UMC can work in 2 modes only, with DRAM. Either 1:1 or 2:1. Past 1900 for RAM the UMC drops to 2:1. The IF can work independently.
Go for DDR4200 (MEMCLK 2100) and you have this:

DRAM(MEMCLK) --> UMC(UCLK) --> IF(FCLK) --> Cores
--------2100 -----------> 1050 -------> 1900 ---> CoreSpeed (3200~4700MHz)

Each one of those sub-parts have their own voltage
1. DDR: DRAM voltage
2. I/O or SoC: CPU SOC voltage
the next two voltages are derived from SoC voltage and cannot be set above or equal to it, but at least 50mV (0.05V) below.
3. UMC: cLDO VDDP voltage
4. IF: cLDO VDDG voltage