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Samsung Delivers Strong 14 nm FinFET Logic Process and Design Infrastructure

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#1
Samsung Electronics Co., Ltd., a global leader in advanced semiconductor solutions, today announced that it reached another milestone in the development of 14-nanometer (nm) FinFET process technology with the successful tape-out of multiple development vehicles in collaboration with its key design and IP partners. In addition, Samsung has signed an agreement with ARM for 14 nm physical IP and libraries. This agreement is the latest in a series from Samsung and ARM that has delivered production proven SoC enablement. Samsung, together with its ecosystem partners, is in a position to offer leading edge customers a robust design infrastructure to drive an ever expanding advanced mobile SoC market.

"As we move closer to true mobile computing, chip designers are eager to take advantage of the gains in performance and significantly lower power of 14 nm FinFET to deliver PC like user experience on a mobile device," said Dr. Kyu-Myung Choi, senior vice president of System LSI infrastructure design center, Device Solutions Division, Samsung Electronics. "The design complexities at 14 nm require complete harmony between the process technology, design methodology, tools and IPs. We are synchronizing all the key elements so our customers can deliver their newest chips to market quickly and efficiently."



As part of its 14 nm FinFET development process, Samsung, and its ecosystem partners - ARM, Cadence, Mentor and Synopsys - taped out multiple test chips ranging from a full ARM Cortex-A7 processor implementation to a SRAM-based chip capable of operation near threshold voltage levels as well as an array of analog IP.

The full ARM Cortex-A7 processor test chip tape-out represents a significant milestone for silicon manufacturing for the fabless ecosystem. The Cortex-A7 implementation on FinFET demonstrates the low-power component of the ARM big.LITTLE processor configuration/technology strategy for mobile computing platforms. The Samsung 14 nm FinFET enablement for SoC design provides improved leakage and dynamic power advantages to the expanding mobile computing market. This collaboration builds on the long-standing partnership between Samsung and ARM including SoC design enablement for the production proven 32/28 nm High-K Metal Gate (HKMG) technology. Enabling SoC design on FinFET allows the continued fast pace of innovation that is the hallmark of the mobile market segment.

The Cortex-A7 processor test chip was implemented by Cadence in collaboration with ARM and Samsung. Cadence delivered a full RTL-to-signoff flow, building upon a tool set that has been thoroughly tested on 20 nm designs requiring automated double patterning. The tight collaboration with Samsung and ARM enabled Cadence to hone its technology for 14 nm FinFET designs, paving the way for 14 nm market readiness. ARM used Cadence tools to develop the 14 nm FinFET libraries, and Cadence tools were also used for a full-flow RTL-to-signoff tapeout of the processor core on Samsung's 14 nm FinFET process, as well as chip-level integration and verification.

Samsung used Synopsys tools optimized for FinFET devices to implement additional IP on this vehicle, including low power SRAMs intended to operate with the power supply close to threshold voltage levels. The move from two-dimensional transistors to three-dimensional transistors introduces several new IP and EDA tool challenges including modeling. The multi-year collaboration between Samsung and Synopsys has delivered foundational modeling technologies for 3D parasitic extraction, circuit simulation and physical design-rule support of FinFET devices.

Samsung is also extending their work with Mentor to enable a complete solution at 14 nm FinFET that addresses customer challenges in design, validation, manufacturing co-optimization, and post-design production ramps. The collaborative efforts leverage the unique capabilities of Samsung's processes, while helping designers deal with the complexities of multi-patterning lithography, FinFET transistors, and more complex reliability requirements.

Silicon-based PDK Availability

With its process design kit available to customers today, customers can start designing with models, design rule manuals and technology files that have been developed based on silicon results from previous 14 nm FinFET test chips run in Samsung's R&D facilities. This PDK includes design flows, routers and other design enablement features to support new device structures, local interconnects, and advanced routing rules. The investments that Samsung is making into the entire ecosystem at 14 nm will give customers early access to all elements of the design infrastructure to accelerate their chip development.
 
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#2
...a global leader in...
This is probably a very rare occasion when this statement actually stands true.

As for the news, i hope this will mean that they'll be able to ramp up core clock and not just stack more cores into the chips...
 
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#4
wow already 14nm, pico meter is in range :)
 

Aquinus

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#5
I wonder how they got around the quantum tunneling problem. At die sizes that small, the channel width on transistors is atoms wide and leakage was said to be pretty extreme.

Glad to see that we're still moving forwards.

Bring it Moore!
 
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Meanwhile, Intel, IBM, Toshiba or TMSC are sleeping...
 
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#7
wow already 14nm, pico meter is in range :)
14nm means the transistor gates are even smaller than that, getting very close to the 1-3nm threshold where quantum tunnelling is a large problem. I'd be surprised if anyone is able to successfully take process nodes below 14nm.

Meanwhile, Intel, IBM, Toshiba or TMSC are sleeping...
Intel is already there. Samsung isn't announcing a processor design, just the process specs with confirmed effectiveness.
 

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14nm means the transistor gates are even smaller than that, getting very close to the 1-3nm threshold where quantum tunnelling is a large problem. I'd be surprised if anyone is able to successfully take process nodes below 14nm.
I agree. I suspect that the multi-gate setup in the FinFETs and Intel's Tri-Gate transistor is mitigating some of the leakage compared to normal single-gate transistors as it reduces resistance by essentially "widening" the channel, it's just cut up into multiple parts. Very soon we're going to come to a point where it can't get any smaller, but that is okay because I'm sure they'll just start stacking dies on top of each other in some form or develop some technology to overcome it regardless of circuit size. Something will happen that will enable Moore's law to hold. I can feel it. It's like it is in the wind or something. :p