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Samsung Delivers Strong 14 nm FinFET Logic Process and Design Infrastructure

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#1
Samsung Electronics Co., Ltd., a global leader in advanced semiconductor solutions, today announced that it reached another milestone in the development of 14-nanometer (nm) FinFET process technology with the successful tape-out of multiple development vehicles in collaboration with its key design and IP partners. In addition, Samsung has signed an agreement with ARM for 14 nm physical IP and libraries. This agreement is the latest in a series from Samsung and ARM that has delivered production proven SoC enablement. Samsung, together with its ecosystem partners, is in a position to offer leading edge customers a robust design infrastructure to drive an ever expanding advanced mobile SoC market.

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#2
...a global leader in...
This is probably a very rare occasion when this statement actually stands true.

As for the news, i hope this will mean that they'll be able to ramp up core clock and not just stack more cores into the chips...
 
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#4
wow already 14nm, pico meter is in range :)
 

Aquinus

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#5
I wonder how they got around the quantum tunneling problem. At die sizes that small, the channel width on transistors is atoms wide and leakage was said to be pretty extreme.

Glad to see that we're still moving forwards.

Bring it Moore!
 
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#6
Meanwhile, Intel, IBM, Toshiba or TMSC are sleeping...
 
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#7
wow already 14nm, pico meter is in range :)
14nm means the transistor gates are even smaller than that, getting very close to the 1-3nm threshold where quantum tunnelling is a large problem. I'd be surprised if anyone is able to successfully take process nodes below 14nm.

Meanwhile, Intel, IBM, Toshiba or TMSC are sleeping...
Intel is already there. Samsung isn't announcing a processor design, just the process specs with confirmed effectiveness.
 

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#8
14nm means the transistor gates are even smaller than that, getting very close to the 1-3nm threshold where quantum tunnelling is a large problem. I'd be surprised if anyone is able to successfully take process nodes below 14nm.
I agree. I suspect that the multi-gate setup in the FinFETs and Intel's Tri-Gate transistor is mitigating some of the leakage compared to normal single-gate transistors as it reduces resistance by essentially "widening" the channel, it's just cut up into multiple parts. Very soon we're going to come to a point where it can't get any smaller, but that is okay because I'm sure they'll just start stacking dies on top of each other in some form or develop some technology to overcome it regardless of circuit size. Something will happen that will enable Moore's law to hold. I can feel it. It's like it is in the wind or something. :p