Well, if you look more closely you'll see the 12MB (on some models 16MB) L3 shared cache. Because you can clearely see the three dual core formations, you think the L3 cache is positioned after the system bus, but that's not true. The scheme is cores(w/L1) -> 3MB L2 cache (per dual core formation) -> 12/16 MB L3 cache -> system bus. Just because it is based on aging FSB architecture doesn't mean the design is not a true six-core.
Don't be fooled into thinking that AMD has a magical solution to avoid data transfers on the HT bus. There are times where this helps a lot, but most of the times, it doesn't help one bit. Not everything will fit into the cache. Actually, most of the time, data will not be "shared" internally by the cores and will actually be sent via the system bus (FSB, QPI or HT, whatever that is). I brought it up because in multi-processor servers the "true n-cores design" is very small because data will more times then you'd imagine be in transit on the system bus.
Dunnington may not be a very elegant design. But in commercial workload benchmarks will destroy AMD chips. Even if it's on FSB. AMD may have "design elegance" on their side, but they have a really hard time exploiting that elegance. In the server world, raw numbers are what matters, elegance is for artists.