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Zen 3: 32MB cache(current) vs 64MB

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What are your thoughts on the announcement by AMD? Why increase the cache while keeping the CPUs the same?

I think it might prove to be a losing move over a whole new generation by Intel(Alder Lake), which is also getting a die shrink.

I was also going to say "why do it now, and not at Zen 3 launch?", but I think the answer to that is vertical stacking; it must have been difficult/impossible to put that much amount of cache on the original versions of Zen 3 processors. But still, why go with only that? Why not launch Zen 4? It seems like a compromise/stepping stone to me.
 
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I've always looked at Zen 3 as mostly being Zen 2 with a re-engineered cache.

That said, cache is very important in latency sensitive use cases and doubly so where it has to take the additional load due to the CCD architecture AMD uses.

In the real world that performance is, IMO, all that matters.

However, Zen 2 / 3 and now 4 are not all new microarchitectures. You really don't get those every couple of years, even though the media and fan bases will say it is all new.

Again though, none of that minutia matters if they can get the performance out.

+10-15% in gaming from a CPU is pretty significant and indicates they have shaved a lot of latency off. That may not translate into other types of applications (productivity) where latency isn't a big issue. Also need a very fast very expensive GPU to make use of that in a game.
 

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3D cache will get only in 12 and 16-core CPUs with 2 CCXs. The 8-core or less CPUs don't need so much cache, or the increase in performance is too small for the higher cost and power draw. My 5c.
 
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What are your thoughts on the announcement by AMD? Why increase the cache while keeping the CPUs the same?

AMD seems to be on a core / uncore cadance, similar to Intel's old "tick tock" cycle.

AMD makes changes to the core (Zen 1), then the uncore / caches (Zen2), then the core (Zen3), then the uncore / caches (Zen3+SRAM stacking)

Zen3 actually had a pretty drastic change to the uncore though, lol. But the idea is to minimize the changes you do from each generation, to minimize the amounts of mistakes that may occur in any given generation. These are pretty complicated machines: you'd hate to be debugging two performance issues simultaneously if something bad happened.
 
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