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AMD Capilano

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Capilano
Block Diagram
Block Diagram
AMD's Capilano GPU uses the TeraScale 2 architecture and is made using a 40 nm production process at TSMC. With a die size of 104 mm² and a transistor count of 627 million it is a small chip. Capilano supports DirectX 11.2 (Feature Level 11_0). It features 400 shading units, 20 texture mapping units and 8 ROPs.
Further reading: Evergreen Series Instruction Set Architecture

Graphics Processor

GPU Name
Capilano
Architecture
TeraScale 2
Foundry
TSMC
Process Size
40 nm
Transistors
627 million
Density
6.0M / mm²
Die Size
104 mm²
Released
Oct 28th, 2009

Graphics Features

DirectX
11.2 (11_0)
OpenGL
4.4
OpenCL
1.2
Vulkan
N/A
Shader Model
5.0
Compute
GFX4

Render Config

Shading Units
400
TMUs
20
ROPs
8
Compute Units
5
Z-Stencil
40
L1 Cache
8 KB per CU
L2 Cache
256 KB
Max. TDP
30 W

All TeraScale 2 GPUs

AMD GPU Architecture History

Graphics cards using the AMD Capilano GPU

Name Chip Memory Shaders TMUs ROPs GPU Clock Memory Clock
AMD Radeon HD 6550M Capilano PRO 1024 MB 400 20 8 600 MHz 900 MHz
AMD Radeon HD 6530M Capilano LE 1024 MB 400 20 8 450 MHz 900 MHz
AMD Radeon HD 6570M Capilano XT 1024 MB 400 20 8 650 MHz 900 MHz
AMD Radeon HD 6570M Mac Edition Capilano XT 1024 MB 400 20 8 600 MHz 800 MHz

Capilano GPU Notes

Architecture Codename: Evergreen
Chip Variant: Redwood
Graphics/Compute: GFX4
Display Core Engine: 4.0
Unified Video Decoder: 2.3