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AMD Cedar

Default
Cedar
Cedar PRO
Cedar PRO
Block Diagram
Block Diagram
AMD's Cedar GPU uses the TeraScale 2 architecture and is made using a 40 nm production process at TSMC. With a die size of 59 mm² and a transistor count of 292 million it is a very small chip. Cedar supports DirectX 11.2 (Feature Level 11_0). For GPU compute applications, OpenCL version 1.2 can be used. It features 80 shading units, 8 texture mapping units and 4 ROPs.
Further reading: Evergreen Series Instruction Set Architecture

Graphics Processor

Released
Jan 31st, 2011
GPU Name
Cedar
Mobile Variant
Park / Robson
Generation
Evergreen
Architecture
TeraScale 2
Foundry
TSMC
Process Size
40 nm
Transistors
292 million
Density
4.9M / mm²
Die Size
59 mm²
Package
FCBGA-631

Graphics Features

DirectX
11.2 (11_0)
OpenGL
4.4
OpenCL
1.2
Vulkan
N/A
Shader Model
5.0
WDDM
1.3
Compute
GFX4
DCE
4.0
UVD
2.3

Render Config

Shading Units
80
TMUs
8
ROPs
4
Compute Units
2
Z-Stencil
4
L1 Cache
8 KB per CU
L2 Cache
128 KB
Max. TDP
25 W

All TeraScale 2 GPUs

AMD GPU Architecture History

Graphics cards using the AMD Cedar GPU

Name Chip Memory Shaders TMUs ROPs GPU Clock Memory Clock
Cedar PRO 512 MB 80 8 4 650 MHz 500 MHz
512 MB 80 8 4 650 MHz 800 MHz
Cedar WS 512 MB 80 8 4 600 MHz 600 MHz
512 MB 80 8 4 650 MHz 800 MHz
1024 MB 80 8 4 650 MHz 667 MHz
Cedar PRO 512 MB 80 8 4 650 MHz 500 MHz
Cedar LE 1024 MB 80 8 4 650 MHz 800 MHz
512 MB 80 8 4 650 MHz 500 MHz
Cedar PRO 1024 MB 80 8 4 650 MHz 533 MHz
Cedar WS 512 MB 80 8 4 600 MHz 600 MHz

Cedar GPU Notes

Generation: Evergreen
Mobile Variant: Park / Robson
Graphics/Compute: GFX4
Display Core Engine: 4.0
Unified Video Decoder: 2.3
Apr 18th, 2024 03:01 EDT change timezone

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