NVIDIA Tesla M2090
The Tesla M2090 was a professional graphics card by NVIDIA, launched in July 2011. Built on the 40 nm process, and based on the GF110 graphics processor, the card supports DirectX 11.0. The GF110 graphics processor is a large chip with a die area of 520 mm² and 3,000 million transistors. It features 512 shading units, 56 texture mapping units and 48 ROPs. NVIDIA has placed 6,144 MB GDDR5 memory on the card, which are connected using a 384-bit memory interface. The GPU is operating at a frequency of 650 MHz, memory is running at 925 MHz.
We recommend the NVIDIA Tesla M2090 for gaming with highest details at resolutions up to, and including, 1680x1050.Being a dual-slot card, the NVIDIA Tesla M2090 draws power from 1x 6-pin + 1x 8-pin power connectors, with power draw rated at 250 W maximum. Tesla M2090 is connected to the rest of the system using a PCIe 2.0 x16 interface. The card measures 248 mm in length, and features a dual-slot cooling solution.
|Process Size:||40 nm|
|Die Size:||520 mm²|
|Released:||Jul 25th, 2011|
|Bus Interface:||PCIe 2.0 x16|
|GPU Clock:||650 MHz|
|Shader Clock:||1300 MHz|
3700 MHz effective
|Memory Size:||6144 MB|
|Memory Bus:||384 bit|
|Pixel Rate:||20.80 GPixel/s|
|Texture Rate:||36.4 GTexel/s|
|Floating-point performance:||1,331.2 GFLOPS|
|Power Connectors:||1x 6-pin + 1x 8-pin|
|Find graphics card BIOS for this card.|
|Find GPU-Z validations for this card.|
GF110 GPU Notes
|Each Streaming Multiprocessor(SM) in the GPU architecture contains 32 SPs and 4 SFUs.
Each SP can fulfill up to two single precision operations FMA per clock.
Each SFU can fulfill up to four SF operations per clock.
The approximate ratio of operations FMA to operations SF is equal 4:1.
The theoretical shader performance in single-precision floating point operations(FMA)[FLOPSsp, GFLOPS] of the graphics card with shader count [n] and shader frequency [f, GHz], is estimated by the following: FLOPSsp f × n × 2.
Alternative formula: FLOPSsp f × m × (32 SPs × 2(FMA)). [m] - SM count.
Total Processing Power: FLOPSsp f × m × (32 SPs × 2(FMA) + 4 × 4 SFUs) or FLOPSsp f × n × 2.5.
Each SM in the GPU contains 4 texture filtering units for every texture address unit.
The complete die contains 64 texture address units and 256 texture filtering units.