News Posts matching #300 mm wafer

Return to Keyword Browsing

Bosch Unveils One Billion Euro Chip Manufacturing Facility in Germany

Robert Bosch GmbH, commonly known as just Bosch, has today unveiled the results of the company's biggest investment ever. On Monday, the company has unveiled its one billion Euro manufacturing facility, which roughly translates to 1.2 billion US Dollars. The manufacturing plant is located in Dresden, Germany, and it aims to supply the leading self-driving automobile companies with chips that are in great demand. As the main goal for the plant is to manufacture chips for the automotive industry, this new 7,200 m² Dresden facility is supposed to provide car makers with Application-Specific Integrated Circuits (ASICs) for power management and tasks such as triggering the automatic braking system of cars.

The one billion Euro facility was funded partly by the funds coming from the European Union investment scheme, which donated as much as 200 million Euros ($243 million). The goal of the plan is to start with the manufacturing of chips for power tools as early as July and start production of automotive chips in September. All of the chips will be manufactured on 300 mm wafers, which offers a major improvement in quantity compared to 200 and 150 mm wafers currently used by Bosch. The opening of this facility will surely help with the global chip shortages, which have even hit the automotive sector.

GLOBALFOUNDRIES and GlobalWafers Partnering to Expand Semiconductor Wafer Supply

GLOBALFOUNDRIES (GF ), the global leader in feature-rich semiconductor manufacturing, and GlobalWafers Co., Ltd. (GWC), one of the top silicon wafer manufacturers in the world, today announced an $800 million agreement to add 300 mm silicon-on-insulator (SOI) wafer manufacturing and expand existing 200 mm SOI wafer production at GWC's MEMC facility in O'Fallon, Missouri.

The silicon wafers produced by GWC are key input materials for semiconductors and an integral part of GF's supply chain. The wafers are used in GF's multi-billion dollar manufacturing facilities, or fabs, where they are used to manufacture the computer chips that are pervasive and vital to the global economy. Today's announcement expands GF's domestic silicon wafer supply from the United States.

UMC Investing $3.6 billion on 28 nm Manufacturing Capabilities Amidst Worldwide Semiconductor Shortages

UMC has announced plans to invest $3.6 billion in increasing output from its 28 nm manufacturing facilities. This move comes amidst a global semiconductor shortage, and isn't the first time a semiconductor manufacturer "dust off" their older manufacturing processes as a way to remove pressure from more modern silicon manufacturing capabilities. In this case, UMC will be increasing manufacturing output from its 300 mm Fab 12A facility in Tainan, Taiwan.

UMC has entered agreements with some of its clients, who will be paying upfront for expected chip rollout in the future. In exchange, clients will get the benefits of preset pricing (thus avoiding any potential increases arising from increased demand or general price fluctuation), as well as UMC's assurance of certain manufacturing volume allocation towards their needs. Fab 12A currently manufactures 90,000 300 mm wafers per month (wpm). An additional 10,000 wpm is being installed this year and phase six will add another 27,500 wpm to the mix. The mature 28 nm tools will be installed in floors that already feature support for future tooling upgrades to 14 nm. UMC expects to hire around 1,000 additional employees as part of this expansion effort.

China Forecast to Represent 22% of the Foundry Market in 2020, says IC Insights

IC Insights recently released its September Update to the 2020 McClean Report that presented the second of a two-part analysis on the global IC foundry industry and included a look at the pure-play foundry market by region.

China was responsible for essentially all of the total pure-play foundry market increase in 2018. In 2019, the U.S./China trade war slowed China's economic growth but its foundry marketshare still increased by two percentage points to 21%. Moreover, despite the Covid-19 shutdown of China's economy earlier this year, China's share of the pure-play foundry market is forecast to be 22% in 2020, 17 percentage points greater than it registered in 2010 (Figure 1).

GLOBALFOUNDRIES Ceases Operations in its Chengdu Fab

GLOBALFOUNDRIES ceased all operations in its joint-venture fab in Chengdu, China. The fab opened its doors in 2018, and was supposed to mass-produce 300 mm wafers on the 22FDX technology in a 65,000 square meter facility. The company's Chinese partner, the Chengdu Municipality, had at the time boasted of investments into the fab peaking at $10 billion. The two had also announced $2 billion in initial design wins.

GloFo's announcement to cease operations and possibly withdraw from Chengdu comes hot on the heals of a separate announcement bolstering its mainland US based facilities up to US-DoD specs for secure manufacturing, a sign that the company will scale up investment into US-based facilities. GloFo's foreshadowed withdrawal from manufacturing in China is part of the ongoing "tech war" between the US and China, with the US getting American (and West-aligned) tech companies to pull manufacturing out of China, the biggest casualties of which is Huawei.

Toshiba and Western Digital Readying 128-layer 3D NAND Flash

Toshiba and its strategic ally Western Digital are readying a high-density 128-layer 3D NAND flash memory. In Toshiba's nomenclature, the chip will be named BiCS-5. Interestingly, despite the spatial density, the chip will implement TLC (3 bits per cell), and not the newer QLC (4 bits per cell). This is probably because NAND flash makers are still spooked about the low yields of QLC chips. Regardless, the chip has a data density of 512 Gb. With 33% more capacity than 96-layer chips, the new 128-layer chips could hit commercial production in 2020-21.

The BiCS-5 chip reportedly features a 4-plane design. Its die is divided into four sections, or planes, which can each be independently accessed; as opposed to BiCS-4 chips that use a 2-plane layout. This reportedly doubles the write performance per unit-channel to 132 MB/s from 66 MB/s. The die also reportedly uses CuA (circuitry under array), a design innovation in which logic circuitry is located in the bottom-most "layer," with data layers stacked above, resulting in 15 percent die-size savings. Aaron Rakers, a high-technology industry market analyst with Wells Fargo, estimates that Toshiba-WD's yields per 300 mm wafer could be as high as 85 percent.

TSMC Fab 14 B Hit With Chemical Contamination; NVIDIA, MEDIATEK, Huawei, Hisilicon Lines Affected

TSMC's Fab 14 B has been affected with a chemical contamination that has put a considerable number of wafers in suspend mode. Fab 14 B essentially produces 12 and 16 nm, 300 mm wafers for 14 companies, including NVIDIA, MEDIATEK, Huawei and Hisilicon. Reportedly, between 10,000 and 30,000 wafers have been affected (though not scrapped, so there might be salvageable bits and pieces here and there). Of course, every wafer will have to go through a thorough certification process, and the fab will have to go down for the company to purge any remains of these botched chemical compounds.

To put things into perspective, though, Fab 14 B is one of TSMC's Gigafabs, which have a rated monthly output of 100k wafers - so production worth between three and ten days could be affected already, with the additional downtime accruing lost potential fabrication. This event isn't expected to significantly affect availability of any of the products for any of the companies, but these are becoming, at the very least, late inventory - this could well play into some speculative increases in pricing from some players in the market.

Q4 2017 300 mm Silicon Wafer Pricing to Increase 20% YoY in DRAM-like Squeeze

Silicon wafers are definitely the best kind of wafers for us tech enthusiasts, but as we all know, required financial resources for the development and production of these is among the most intensive in development costs and R&D. It's not just about the cost of employing enough (and crucially, good enough) engineers that can employ the right tools and knowledge to design the processing miracles that are etched onto wafers; there's also the cost of good, old production as well. Extreme Ultraviolet Lithography Systems that are used for the production of silicon wafers are about the size of a city bus, and typically cost more than 100 million euros ($115.3 million) each. ASML, a Dutch company that specializes in this kind of equipment, announced this year it was expecting to see a 25% revenue growth for 2017. Increased demand for these systems - and added cost of development of ever increasingly small and complex etchings in wafers - means this sector is seeing strong growth. But where there is strong growth, there is usually high demand, and high demand means higher strain on supply, which may sometimes not be able to keep up with the market's needs.

This is seemingly the case for wafer pricing; as demand for wafer production has been increasing, so to are prices. Faced with increased demand, companies are usually faced with a tough question to answer in regards to the correct course of action. Usually, it goes like this: higher demand at the same supply level means higher pricing. However, if supply isn't enough to satisfy demand, manufacturers are losing out on potential increased sales. This leads most companies to increase supply relative to demand, but always with lower projected output than demand requires, so they can bask in both increased ASP (Average Sale Price) and higher number of sales. This has been the case with DRAM memory production for some time now: and is happening with 300 mm silicon wafers as well.
Return to Keyword Browsing