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Intel Ponte Vecchio GPU to Be Liquid Cooled Inside OAM Form Factor

Intel's upcoming Ponte Vecchio graphics card is set to be the company's most powerful processor ever designed, and the chip is indeed looking like an engineering marvel. From Intel's previous teasers, we have learned that Ponte Vecchio is built using 47 "magical tiles" or 47 dies which are responsible either for computing elements, Rambo Cache, Xe links, or something else. Today, we are getting a new piece of information coming from Igor's LAB, regarding the Ponte Vecchio and some of its design choices. For starters, the GPU will be a heterogeneous design that consists out of many different nodes. Some parts of the GPU will be manufactured on Intel's 10 nm SuperFin and 7 nm technologies, while others will use TSMC's 7 nm and 5 nm nodes. The smaller and more efficient nodes will probably be used for computing elements. Everything will be held together by Intel's EMIB and Foveros 3D packaging.

Next up, we have information that this massive Intel processor will be accountable for around 600 Watts of heat output, which is a lot to cool. That is why in the leaked renders, we see that Intel envisioned these processors to be liquid-cooled, which would make the cooling much easier and much more efficient compared to air cooling of such a high heat output. Another interesting thing is that the Ponte Vecchio is designed to fit inside OAM (OCP Accelerator Module) form factor, an alternative to the regular PCIe-based accelerators in data centers. OAM is used primarily by hyper scalers like Facebook, Amazon, Google, etc., so we imagine that Intel already knows its customers before the product even hits the market.

AMD Shares New Details on Their 3D V-Cache Tech for Zen 3+

AMD via its official YouTube has shared a video that goes into slightly more detail on their usage of V-Cache on the upcoming Zen 3+ CPUs. Firstly demoed to the public on AMD's Computex 2021 event, the 3D V-Cache leverages TSMC's SoIC stacking technology, which enables silicon developments along the Z axis, instead of the more usual footprint increase along the X axis. The added 3D V-Cache, which was shown in Computex as being deployed in a prototype Ryzen 9 5900X 12-core CPU, adds 64 MB of L3 cache to each CCX (the up-to-eight-cores core complex on AMD's latest Zen design), basically tripling the amount of L3 cache available for the CPU. This, in turn, was shown to increase FPS in games quite substantially (somewhere around 15%), as games in particular are sensitive to this type of CPU resources.

The added information explains that there is no usage of microbumps - instead, there is a perfect alignment between the bottom layer (with the CCX) and the top layer (the L3 cache) which enables the bonding process to occur naturally via the TSVs (Through Silicon Vias) already present in the silicon, in a zero-gap manner, between both halves of the CPU-cache sandwich. To enable this, AMD flipped the CCX upside down (the core complex now faces the bottom of the chip, instead of the top), shaved 95% of the silicon on top of the upside-down core complexes, and then attaches the 3D V-Cache chips on top of this formation. This also has the added bonus of decreasing the distance between the L3 cache and the CCX (the distance between both in the Z axis is around 1,000 times smaller than if the L3 cache was deployed in the classical X axis), which decreases power consumption, temperatures, and latency, allowing for further increases to system performance. Look after the break for the full video.

AMD "Milan-X" Processor Could Use Stacked Dies with X3D Packaging Technology

AMD is in a constant process of processor development, and there are always new technologies on the horizon. Back in March of 2020, the company has revealed that it is working on new X3D packaging technology, that integrated both 2.5D and 3D approaches to packing semiconductor dies together as tightly as possible. Today, we are finally getting some more information about the X3D technology, as we have the first codename of the processor that is featuring this advanced packaging technology. According to David Schor, we have learned that AMD is working on a CPU that uses X3D tech with stacked dies, and it is called Milan-X.

The Milan-X CPU is AMD's upcoming product designed for data center usage. The rumors suggest that the CPU is designed for heavy bandwidth and presumably a lot of computing power. According to ExecutableFix, the CPU uses a Genesis-IO die to power the connectivity, which is an IO die from EPYC Zen 3 processors. While this solution is in the works, we don't know the exact launch date of the processor. However, we could hear more about it in AMD's virtual keynote at Computex 2021. For now, take this rumor with a grain of salt.
AMD X3D Packaging Technology

SK Hynix Envisions the Future: 600-Layer 3D NAND and EUV-made DRAM

On March 22nd, the CEO of SK Hynix, Seok-Hee Lee, gave a keynote speech to the IEEE International Reliability Physics Symposium (IRPS) and shared with experts a part of its plan for the future of SK Hynix products. The CEO took the stage and delivered some conceptual technologies that the company is working on right now. At the center of the show, two distinct products stood out - 3D NAND and DRAM. So far, the company has believed that its 3D NAND scaling was very limited and that it can push up to 500 layers sometime in the future before the limit is reached. However, according to the latest research, SK Hynix will be able to produce 600-layer 3D NAND technology in the distant future.

So far, the company has managed to manufacture and sample 512Gb 176-layer 3D NAND chips, so the 600-layer solutions are still far away. Nonetheless, it is a possibility that we are looking at. Before we reach that layer number, there are various problems needed to be solved so the technology can work. According to SK Hynix, "the company introduced the atomic layer deposition (ALD) technology to further improve the cell property of efficiently storing electric charges and exporting them when needed, while developing technology to maintain uniform electric charges over a certain amount through the innovation of dielectric materials. In addition to this, to solve film stress issues, the mechanical stress levels of films is controlled and the cell oxide-nitride (ON) material is being optimized. To deal with the interference phenomenon between cells and charge loss that occur when more cells are stacked at a limited height, SK Hynix developed the isolated-charge trap nitride (isolated-CTN) structure to enhance reliability."

ADATA Explains Changes with XPG SX8200 Pro SSD

ADATA has recently been in a spot of controversy when it comes to their XPG SX8200 Pro solid-state drive (SSD). The company has reportedly shipped many different configurations of the SSD with different drive controller clock speeds and different NAND flash. According to the original report, ADATA has first shipped the SX8200 Pro SSD with Silicon Motion SM2262ENG SSD controller, running at 650 MHz with IMFT 64-layer TLC NAND Flash. However, it was later reported that the SSD was updated to use the Silicon Motion SM2262G SSD controller, clocked at 575 MHz. With this report, many users have gotten concerned and started to question the company's practices. However, ADATA later ensured everyone that performance is within the specifications and there is no need to worry.

Today, we have another report about the ADATA XPG SX8200 Pro SSD. According to a Redditor, ADATA has once again updated its SSD with a different kind of NAND Flash, however, this time the report indicated that performance was impacted. Tom's Hardware has made a table of changes showing as many as five revisions of the SSD, all with different configurations of SSD controllers and NAND Flash memory. We have contacted ADATA to clarify the issues that have emerged, and this is the official response that the company gave us.

Kioxia and Western Digital Announce 6th-Generation 162-layer 3D NAND Flash Memory

Kioxia Corporation and Western Digital Corp., today announced that the companies have developed their sixth-generation, 162-layer 3D flash memory technology. Marking the next milestone in the companies' 20-year joint-venture partnership, this is the companies' highest density and most advanced 3D flash memory technology to date, utilizing a wide range of technology and manufacturing innovations.

"Through our strong partnership that has spanned two decades, Kioxia and Western Digital have successfully created unrivaled capabilities in manufacturing and R&D," said Masaki Momodomi, Chief Technology Officer, Kioxia. "Together, we produce over 30 percent of the world's flash memory bits and are steadfast in our mission to provide exceptional capacity, performance and reliability at a compelling cost. We each deliver this value proposition across a range of data-centric applications from personal electronics to data centers as well as emerging applications enabled by 5G networks, artificial intelligence and autonomous systems."

TSMC Partners With Google and AMD to Push 3D Silicon

Silicon manufacturing is starting to get harder and harder every day, with new challenges appearing daily. It requires massive investment and massive knowledge to keep a silicon manufacturing company afloat. No company can survive that alone, so some collaborations are emerging. Today, thanks to the sources of Nikkei Asia, we have information that Taiwanese Semiconductor Manufacturing Company (TSMC) is collaborating with Google to push the production of 3D chip manufacturing process, that is said to overcome some of the silicon manufacturing difficulties. The sources also say that AMD is involved in the process as well, making Google and AMD the first customers of the advanced 3D chip design. The two companies are preparing designs for the new way of creating silicon and will help TSMC test and certify the process.

TSMC will deploy the 3D silicon manufacturing technology at its chip packaging plant in Miaoli, which is supposed to do mass production in 2022. With Google and AMD being the first customers of new 3D technology, it is exciting to see what new products will look like and how they will perform. The 3D approach is said to bring huge computing power increase, however, it is a waiting game now to see how it will look like.

Basemark Launches GPUScore Relic of Life RayTracing Benchmark

Basemark is pioneer in GPU benchmarking. Our current product Basemark GPU has been improving the 3D graphics industry since 2016. After releasing GPU 1.2 in March Basemark development team has been really busy developing brand new benchmark - GPUScore. GPUScore benchmark will introduce hyper realistic, true gaming type of content in three different workloads: Relic of Life, Sacret Path and Expedition.

GPUScore Relic of Life is targeted to benchmark high end graphics cards. It is completely new benchmark with many new features. The key new feature is real-time ray traced reflections and reflections of reflections. The benchmark will not only support Windows & DirectX 12, but also Linux & Vulkan raytracing.

AMD Graphics Drivers Have a CreateAllocation Security Vulnerability

Discovering vulnerabilities in software is not an easy thing to do. There are many use cases and states that need to be tested to see a possible vulnerability. Still, security researchers know how to find those and they usually report it to the company that made the software. Today, AMD has disclosed that there is a vulnerability present in the company graphics driver powering the GPUs and making them work on systems. Called CreateAllocation (CVE-2020-12911), the vulnerability is marked with a score of 7.1 in the CVSSv3 test results, meaning that it is not a top priority, however, it still represents a big problem.

"A denial-of-service vulnerability exists in the D3DKMTCreateAllocation handler functionality of AMD ATIKMDAG.SYS 26.20.15029.27017. A specially crafted D3DKMTCreateAllocation API request can cause an out-of-bounds read and denial of service (BSOD). This vulnerability can be triggered from a guest account, " says the report about the vulnerability. AMD states that a temporary fix is implemented by simply restarting your computer if a BSOD happens. The company also declares that "confidential information and long-term system functionality are not impacted". AMD plans to release a fix for this software problem sometime in 2021 with the new driver release. You can read more about it here.

TSMC Begins Construction of 2 nm Manufacturing Facility

TSMC, the leading semiconductor foundry in the world, has reportedly begun construction of its 2 nm manufacturing facility. According to a DigiTimes report, translated by @chiakokhua on Twitter, besides the construction of 2 nm R&D center, TSMC has also started the construction of the manufacturing facility for that node, so it will be ready in time. Please do note that the node name doesn't represent the size of the transistor, so it will not actually be 2 nm wide. The new facilities will be located near TSMC's headquarters in Hsinchu Science Park, Taiwan. The report also confirms the first details about the node, specifically that it will use Gate-All-Around (GAA) technology. And there is also another interesting piece of information regarding even smaller node, the planning for 1 nm node has begun according to the source.

Besides advanced nodes, TSMC also laid out clear plans to accelerate the push of advanced packaging technology. That includes SoIC, InFO, CoWoS, and WoW. All of these technologies are classified as "3D Fabric" by the company, even though some are 2.5D. These technologies will be mass-produced at "ZhuNan" and "NanKe" facilities starting in the second half of 2021, and are expected to significantly contribute to the company's profits. It is also reported that the competing foundry, Samsung, has a 3D packaging technology of its own called X-cube, however, it is attracting customers a lot slower than TSMC due to the high costs of the new technology.

Rambus Advances HBM2E Performance to 4.0 Gbps for AI/ML Training Applications

Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it has achieved a record 4 Gbps performance with the Rambus HBM2E memory interface solution consisting of a fully-integrated PHY and controller. Paired with the industry's fastest HBM2E DRAM from SK hynix operating at 3.6 Gbps, the solution can deliver 460 GB/s of bandwidth from a single HBM2E device. This performance meets the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI/ML training and high-performance computing (HPC) applications.

"With this achievement by Rambus, designers of AI and HPC systems can now implement systems using the world's fastest HBM2E DRAM running at 3.6 Gbps from SK hynix," said Uksong Kang, vice president of product planning at SK hynix. "In July, we announced full-scale mass-production of HBM2E for state-of-the-art computing applications demanding the highest bandwidth available."

COVID-19 Drives Rise in Global Fab Equipment Spending, SEMI Reports

Soaring pandemic-inspired demand for chips that power everything from communications and IT infrastructures to personal computing, gaming and healthcare electronics will drive an 8% increase in global fab equipment spending in 2020 and a 13% increase in 2021, SEMI announced today in its World Fab Forecast report. Rising demand for semiconductors for datacenter infrastructures and server storage along with the buildup of safety stock as U.S.-China trade tensions intensify are also contributing to this year's growth.

The bullish trend for overall fab equipment investments comes as the semiconductor industry recovers from a 9% decline in fab spending in 2019 and navigates a roller-coaster 2020 with actual and projected spending drops in the first and third quarters mixed with second- and fourth-quarter increases. See figure below:

AMD Preparing Additional Ryzen 4000G Renoir series SKUs, Ryzen 7 Pro 4750G Benchmarked

AMD Ryzen 4000 series of desktop APUs are set to be released next month as a quiet launch. What we expected to see is a launch covering only a few models ranging from Ryzen 3 to Ryzen 7 level, meaning that there would be configurations equipped with anything from 4C/8T to 8C/16T. In the beginning thanks to all the leaks we expected to see six models (listed in the table below), however thanks to discovery, we could be looking at even more SKUs of the Renoir family of APUs. Mentioned in the table are some new entries to both consumer and pro-grade users which means AMD will probably do a launch of both editions, possibly on the same day. We are not sure if that is the case, however, it is just a speculation.
AMD Ryzen 4000G Renoir SKUs

Micron Delivers Client NVMe Performance and Value SSDs With Industry-Leading Capacity Sizes and QLC NAND

Micron Technology, Inc., today announced new client solid-state drives (SSDs) that bring NVMe performance to client computing applications, freeing laptops, workstations and other portables from legacy architectures that can rob devices of battery power, performance and productivity. The Micron 2300 SSD combines the power and density needed to drive compute-heavy applications in a compact form factor with the reduced power consumption modern mobile users demand. For the first time, Micron brings together NVMe performance and low-cost quad-level-cell (QLC) NAND in the Micron 2210 QLC SSD. It combines fast NVMe throughput and Micron's leadership in QLC technology to offer flash capabilities at hard disk drive-like price points while reducing power consumption by 15 times when compared to hard drives.
Micron 2300 NVMe SSD

Intel's Alder Lake Processors Could use Foveros 3D Stacking and Feature 16 Cores

Intel is preparing lots of interesting designs for the future and it is slowly shaping their vision for the next generation of computing devices. Following the big.LITTLE design principle of Arm, Intel decided to try and build its version using x86-64 cores instead of Arm ones, called Lakefield. And we already have some information about the new Alder Lake CPUs based on Lakefield design that are set to be released in the future. Thanks to a report from Chrome Unboxed, who found the patches submitted to Chromium open-source browser, used as a base for many browsers like Google Chrome and new Microsoft Edge, there is a piece of potential information that suggests Alder Lake CPUs could arrive very soon.

Rumored to feature up to 16 cores, Alder Lake CPUs could present an x86 iteration of the big.LITTLE design, where one pairs eight "big" and eight "small" cores that are activated according to increased or decreased performance requirements, thus bringing the best of both worlds - power efficiency and performance. This design would be present on Intel's 3D packaging technology called Foveros. The Alder Lake CPU support patch was added on April 27th to the Chrome OS repository, which would indicate that Intel will be pushing these CPUs out relatively quickly. The commit message titled "add support for ADL gpiochip" contained the following: "On Alderlake platform, the pinctrl (gpiochip) driver label is "INTC105x:00", hence declare it properly." The Chrome Unboxed speculates that Alder Lake could come out in mid or late 2021, depending on how fast Intel could supply OEMs with enough volume.
Intel Lakefield

BenQ Launches SW321C 32-inch Monitor

BenQ today announced the latest addition to its monitor family design for professional use. The SW321C, as it is called, is a 32-inch monitor with an IPS panel of 4K (3840×2160p) resolution. The panel itself is a 60 Hz screen with 250 nits of brightness, 1000:1 contrast ratio, 5 ms GtG response time, and it offers 178-degree viewing angles, which is standard for IPS panels. When it comes to the color coverage and the ability to accurately represent them, the SW321C features 95% of the DCI-P3, 99% of the Adobe RGB, and 100% of the sRGB color gamut. It has a 16-bit 3D look-up table (LUT) and features calibration for DeltaE ≤ 2.

The monitor comes with HDR10 specification, however, due to the brightness of 250 nits, it is not capable of performing any serious HDR content editing. Another interesting note is that this monitor supports Hybrid Log-Gamma (HLG) standard, which is an uncommon one. For input, the monitor had support for one DisplayPort 1.4, two HDMI 2.0, and one USB-C port. There is a dual-port USB hub, which has an SD card reader right next to it, making this very useful feature for photographers. Exact pricing and availability of this monitor are unknown, however, it is supposed to hit the market soon.
BenQ SW321C monitor BenQ SW321C monitor BenQ SW321C monitor

Intel and Micron Sign New Agreement for 3D XPoint Shipment

Intel and Micron have signed a new agreement for the production of 3D XPoint memory. As currently the only source of 3D XPoint memory solutions, Micron will get a significant increase in cash flow coming from Intel for the memory production. While Intel and Micron ended their partnership on 3D XPoint memory, they have signed a new contract for the production and supply of new 3D XPoint wafers to Intel. This shows that the demand for 3D XPoint memory is strong, so Intel needs production capacity to deliver the memory, and Micron is the obvious choice.

Previously, Intel sold its ownership of Lehi fab based in Utah, which was manufacturing the 3D XPoint memory solutions, so it was left to Micron to use. However, they signed a new deal and now Micron is in charge of manufacturing and addressing the supply issues for Intel's future Optane products. The new agreement comes with changed pricing and forecast of the sales, so Intel is likely paying more cash to Micron this time.
Intel 3D XPoint

TSMC and Broadcom Enhance the CoWoS Platform with World's First 2X Reticle Size Interposer

TSMC today announced it has collaborated with Broadcom on enhancing the Chip-on-Wafer-on-Substrate (CoWoS ) platform to support the industry's first and largest 2X reticle size interposer. With an area of approximately 1,700mm2, this next generation CoWoS interposer technology significantly boosts computing power for advanced HPC systems by supporting more SoCs as well as being ready to support TSMC's next-generation five-nanometer (N5) process technology.

This new generation CoWoS technology can accommodate multiple logic system-on-chip (SoC) dies, and up to 6 cubes of high-bandwidth memory (HBM), offering as much as 96 GB of memory. It also provides bandwidth of up to 2.7 terabytes per second, 2.7 times faster than TSMC's previously offered CoWoS solution in 2016. With higher memory capacity and bandwidth, this CoWoS solution is well-suited for memory-intensive workloads such as deep learning, as well as workloads for 5G networking, power-efficient datacenters, and more. In addition to offering additional area to increase compute, I/O, and HBM integration, this enhanced CoWoS technology provides greater design flexibility and yield for complex ASIC designs in advanced process nodes.

CEA-Leti Makes a 96 core CPU from Six Chiplets

Chiplet design of processors is getting more popular due to many improvements and opportunities it offers. Some of the benefits include lower costs as the dies are smaller compared to one monolithic design, while you are theoretically able to stitch as much of the chiplets together as possible. During the ISSCC 2020 conference, CEA-Leti, a French research institute, created a 96 core CPU made from six 3D stacked 16 core chiplets. The chip is created as a demonstration of what this modular approach offers and what are the capabilities of the chiplet-based CPU design.

The chiplets are manufactured on the 28 nm FD-SOI manufacturing process from STMicroelectronics, while the active interposer die below them that is connecting everything is made using the 65 nm process. Each one of the six dies is housing 16 cores based on MIPS Instruction Set Architecture core. Each chiplet is split into four 4-core clusters that make up for a total of 16 cores per chiplet. When it comes to the core itself, it is a scalar MIPS32v1 core equipped with 16 KiB of L1 instruction and an L1 data cache. For L2 cache, there is 256 KiB per cluster, while the L3 cache is split into four 1 MiB tiles for the whole cluster. The chiplets are stacked on top of an active interposer which connects the chiplets and provides external I/O support.

VR as a Coping Mechanism for Loss: Meet Nayeon

VR has been hailed as the next coming of truly ingenious, engrossing, enveloping experiences, and to some extent, it already does offer those. There are still limitations to the technology and the level of realism it can impart (there is a whole slew of senses we need to trigger for truly enveloping experiences, of course), but I feel we sometimes get somewhat limited in the way we look at VR. Of course, we can all imagine video games built in VR - and when we do, we likely imagine them as they were presented to us in Steven Spielberg's Ready Player One.

Then there are other use-cases, such as real-estate experiences that place you right inside your future home and allow you to see the changes you'd make. Architecture design, engineering, game world design, even strolls through museums, your mind a subatomic particle able to instantly travel to foreign countries and explore their marvels. All for this, mind you, without ever leaving the comfort of our home, without the required expenses and no wasted time with travelling or passport checks - all, however, simulated. But what if VR could go even further? What if VR could be used as a coping mechanism? What if you could meet your dead parents, siblings... Or children? This is the story I bring to you today: of how VR was used to reunite a mother with her deceased seven-year-old girl. This is the story of Ji-sung and her daughter Nayeon.

SK Hynix Licenses DBI Ultra 3D Interconnect Technology

Xperi Corporation today announced that it entered into a new patent and technology license agreement with SK hynix, one of the world's largest semiconductor manufacturers. The agreement includes access to Xperi's broad portfolio of semiconductor intellectual property (IP) and a technology transfer of Invensas DBI Ultra 3D interconnect technology focused on next-generation memory.

"We are delighted to announce the extension of our long-standing relationship with SK hynix, a world-renowned technology leader and manufacturer of memory solutions," said Craig Mitchell, President of Invensas, a wholly owned subsidiary of Xperi Corporation. "As the industry increasingly looks beyond conventional node scaling and turns toward hybrid bonding, Invensas stands as a pioneering leader that continues to deliver improved performance, power, and functionality, while also reducing the cost of semiconductors. We are proud to partner with SK hynix to further develop and commercialize our DBI Ultra technology and look forward to a wide range of memory solutions that leverage the benefits of this revolutionary technology platform."

Kioxia Corporation Unveils 5th-Generation BiCS FLASH

Kioxia Corporation, the world leader in memory solutions, today announced that it has successfully developed its fifth-generation BiCS FLASH three-dimensional (3D) flash memory with a 112-layer vertically stacked structure. Kioxia plans to start shipping samples of the new device, which has a 512 gigabit (64 gigabytes) capacity with 3-bit-per-cell (triple-level cell, TLC) technology, for specific applications in the first quarter of calendar year 2020. The new device aims to fulfill ever-growing bit demands for a wide variety of applications, including traditional mobile devices, consumer and enterprise SSDs, emerging applications enabled by the new 5G networks, artificial intelligence and autonomous vehicles.

Going forward, Kioxia will apply its new fifth-generation process technology to larger capacity devices, such as 1 terabit (128 gigabytes) TLC and 1.33 terabit 4-bit-per-cell (quadruple-level cell, QLC) devices.

Intel to Detail Xe Graphics Card Architecture at GDC

This year's Game Developers Conference (GDC) that will take place in March is forming to become a very interesting one. According to the GDC schedule platform, Intel is having a presentation about its upcoming Xe graphics card architecture. Saying that "Intel's brand new Xe Architecture, has been teased for a while, and is scheduled for release later this year! This update brings a significant compute, geometry and throughput improvements over today's widely used Gen9 and Gen11 graphics.", Intel is giving us a slight hint of what is to come.

Presented by Intel's senior developer relations engineer, Antonie Cohade, the talk will include an in-depth look of the Xe hardware architecture and its implementations. Said to introduce "powerful new features", the talk about Xe graphics should include a mention of the latest trend in the world of 3D graphics, ray tracing, and show us what are the capabilities of the new GPU architecture.

Kioxia Develops New 3D Semicircular Flash Memory Cell Structure "Twin BiCS FLASH"

Kioxia Corporation today announced the development of the world's first three-dimensional (3D) semicircular split-gate flash memory cell structure "Twin BiCS FLASH" using specially designed semicircular Floating Gate (FG) cells. Twin BiCS FLASH achieves superior program slope and a larger program/erase window at a much smaller cell size compared to conventional circular Charge Trap (CT) cells. These attributes make this new cell design a promising candidate to surpass four bits per cell (QLC) for significantly higher memory density and fewer stacking layers. This technology was announced at the IEEE International Electron Devices Meeting (IEDM) held in San Francisco, CA on December 11th.

3D flash memory technology has achieved high bit density with low cost per bit by increasing the number of cell stacked layers as well as by implementing multilayer stack deposition and high aspect ratio etching. In recent years, as the number of cell layers exceeds 100, managing the trade-offs among etch profile control, size uniformity and productivity is becoming increasingly challenging. To overcome this problem, Kioxia developed a new semicircular cell design by splitting the gate electrode in the conventional circular cell to reduce cell size compared to the conventional circular cell, enabling higher-density memory at a lower number of cell layers.

Intel RealSense Lidar Camera Technology Redefines Computer Vision

Today, Intel announced the Intel RealSense lidar camera L515, the world's smallest and most power-efficient, high-resolution lidar that captures millions of depth points per second. Designed with proprietary technology that creates entirely new ways to incorporate lidar into smart devices to perceive the world in 3D, the L515 provides high-quality performance and millimeter accuracy to products that require vision capabilities.

"Intel RealSense technology is used to develop products that enrich people's lives by enabling machines and devices to perceive the world in 3D. With the L515 depth camera, we are excited to bring high-resolution lidar performance to markets previously inaccessible to this technology."
-Sagi BenMoshe, corporate vice president, Intel RealSense Group
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