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Two AMD Ryzen 7000 Series Processors Based on Zen 4 Core Appear: 16-Core and 8-Core SKUs

AMD's Ryzen 7000 series of desktop processors based on the novel Zen 4 core architecture are scheduled to arrive in the second half of 2022. While we are not sure just how big the architectural differences will be going from Zen 3 (with or without 3D V-cache) to the new Zen 4 core, we have some leaked information that confirms the existence of two SKUs that reveal additional details about the processor configuration. In the MilkyWay@Home project, aiming to create a model of the Milky Way galaxy by utilizing countless PCs across the globe, we found two next-generation Ryzen 7000 SKUs. The MilkyWay@Home project isn't a benchmark. However, it is a valuable reference where the next generation processors appeared.

First in line is the 100-000000666-21_N CPU, a codename for an eight-core, sixteen-threaded design. This model should correspond to the AMD Ryzen 7 7800X CPU, a successor to the Ryzen 7 5800X model. Next in line is the 100-000000665-21_N CPU with 16 cores and 32 threads, a successor to the Ryzen 9 5950X named Ryzen 9 7950X. One important thing to note is that these new CPUs feature different level two (L2) cache configurations. With the previous generation 5000 series "Vermeer" processors, the L2 cache was locked at 512 KB per core. However, according to today's leak, the upgraded Zen 4 IP will bring 1024 KB of L2 cache per core, doubling the cache size at one of the fastest levels.

AMD Will Give a Glimpse of Zen4 Core at CES 2022 Presentation

As the year ends, one of the biggest consumer trade shows, CES, is on the horizon, and manufacturers are ready to present the work that will become real throughout the year. AMD will offer a keynote at the CES 2022 press conference, and we expect to hear more about the upcoming Zen3 processors with 3D V-cache stacked in them. However, what is interesting is that we may listen to more details about Zen4 core. In an exclusive interview conducted by Antony Leather, Forbes contributor and the person behind CrazyTechLab, AMD CTO Mark Papermaster started the hype machine by sharing that AMD will announce some Zen4 core details at the CES 2022 conference.
AMD CTO Mark PapermasterWith regards to the upcoming generation - I point to CES in January. We're excited to be revealing some additional details on our new product launches that will deliver phenomenal experiences and as we've said, later in the year as it progresses we'll share more detail on Zen 4 with some mentioned at CES and more announcements on it over the course of 2022. It will be a very exciting year for AMD.

NAND Flash ASP Expected to Undergo 10-15% QoQ Decline in 1Q22 as Market Shifts Towards Oversupply, Says TrendForce

Demand for NAND Flash products will undergo a noticeable and cyclical downward correction in 1Q22 as major smartphone brands wind down their procurement activities for the peak season and ODMs prepare for the New Year holidays, according to TrendForce's latest investigations. As such, the NAND Flash market will remain in an oversupply situation, with prices continuing to undergo downward corrections accordingly. However, PC OEMs have been reinstating certain orders for client SSDs since early November in response to improvements in the supply of upstream semiconductor materials. By fulfilling these orders, suppliers are able to keep their inventory level relatively low, meaning they are not under as much pressure as previously expected to reduce inventory by lowering prices. Taking these factors into account, TrendForce expects NAND Flash ASP to undergo a 10-15% QoQ decline in 1Q22, during which NAND Flash prices will experience the most noticeable declines compared to the other quarters in 2022.

Regarding the price trend of NAND Flash products across the whole 2021, TrendForce further indicates that suppliers have actively transitioned their output to higher-layer technologies, resulting in a bit supply growth that noticeably outpaces demand, though the tight supply of components such as controller ICs and PMICs has constrained the production of NAND Flash end-products. Hence, the decline in contract prices of NAND Flash products has not been as severe as previously expected. Moving ahead to 2022, however, the supply of relevant components is expected to gradually improve, so the market for various NAND Flash products will also likely shift towards a noticeable oversupply. As a result, prices of NAND Flash products will steadily decline before the arrival of the peak season in 3Q22.

Synopsys Accelerates Multi-Die Designs with Industry's First Complete HBM3 IP and Verification Solutions

Synopsys, Inc. today announced the industry's first complete HBM3 IP solution, including controller, PHY, and verification IP for 2.5D multi-die package systems. HBM3 technology helps designers meet essential high-bandwidth and low-power memory requirements for system-on-chip (SoC) designs targeting high-performance computing, AI and graphics applications. Synopsys' DesignWare HBM3 Controller and PHY IP, built on silicon-proven HBM2E IP, leverage Synopsys' interposer expertise to provide a low-risk solution that enables high memory bandwidth at up to 921 GB/s.

The Synopsys verification solution, including Verification IP with built-in coverage and verification plans, off-the-shelf HBM3 memory models for ZeBu emulation, and HAPS prototyping system, accelerates verification from HBM3 IP to SoCs. To accelerate development of HBM3 system designs, Synopsys' 3DIC Compiler multi-die design platform provides a fully integrated architectural exploration, implementation and system-level analysis solution.

NVIDIA Announces Financial Results for Second Quarter Fiscal 2022

NVIDIA (NASDAQ: NVDA) today reported record revenue for the second quarter ended August 1, 2021, of $6.51 billion, up 68 percent from a year earlier and up 15 percent from the previous quarter, with record revenue from the company's Gaming, Data Center and Professional Visualization platforms. GAAP earnings per diluted share for the quarter were $0.94, up 276 percent from a year ago and up 24 percent from the previous quarter. Non-GAAP earnings per diluted share were $1.04, up 89 percent from a year ago and up 14 percent from the previous quarter.

"NVIDIA's pioneering work in accelerated computing continues to advance graphics, scientific computing and AI," said Jensen Huang, founder and CEO of NVIDIA. "Enabled by the NVIDIA platform, developers are creating the most impactful technologies of our time - from natural language understanding and recommender systems, to autonomous vehicles and logistic centers, to digital biology and climate science, to metaverse worlds that obey the laws of physics.

NVIDIA Founder and CEO Jensen Huang to Receive Prestigious Robert N. Noyce Award

The Semiconductor Industry Association (SIA) today announced Jensen Huang, founder and CEO of NVIDIA and a trailblazer in building accelerated computing platforms, is the 2021 recipient of the industry's highest honor, the Robert N. Noyce Award. SIA presents the Noyce Award annually in recognition of a leader who has made outstanding contributions to the semiconductor industry in technology or public policy. Huang will accept the award at the SIA Awards Dinner on Nov. 18, 2021.

"Jensen Huang's extraordinary vision and tireless execution have greatly strengthened our industry, revolutionized computing, and advanced artificial intelligence," said John Neuffer, SIA president and CEO. "Jensen's accomplishments have fueled countless innovations—from gaming to scientific computing to self-driving cars—and he continues to advance technologies that will transform our industry and the world. We're pleased to recognize Jensen with the 2021 Robert N. Noyce Award for his many achievements in advancing semiconductor technology."

Linux Foundation to Form New Open 3D Foundation

The Linux Foundation, the nonprofit organization enabling mass innovation through open source, today announced an intent to form the Open 3D Foundation to accelerate developer collaboration on 3D game and simulation technology. The Open 3D Foundation will support open source projects that advance capabilities related to 3D graphics, rendering, authoring, and development. As the first project governed by the new foundation, Amazon Web Services, Inc. (AWS) is contributing an updated version of the Amazon Lumberyard game engine as the Open 3D Engine (O3DE), under the permissive Apache 2.0 license. The Open 3D Engine enables developers and content creators to build 3D experiences unencumbered by commercial terms and will provide the support and infrastructure of an open source community through forums, code repositories, and developer events. A developer preview of O3DE is available on GitHub today. For more information and/or to contribute, please visit: https://o3de.org

3D engines are used to create a range of virtual experiences, including games and simulations, by providing capabilities such as 3D rendering, content authoring tools, animation, physics systems, and asset processing. Many developers are seeking ways to build their intellectual property on top of an open source engine where the roadmap is highly visible, openly governed, and collaborative to the community as a whole. More developers look to be able to create or augment their current technological foundations with highly collaborative solutions that can be used in any development environment. O3DE introduces a new ecosystem for developers and content creators to innovate, build, share, and distribute immersive 3D worlds that will inspire their users with rich experiences that bring the imaginations of their creators to life.

Intel Ponte Vecchio GPU to Be Liquid Cooled Inside OAM Form Factor

Intel's upcoming Ponte Vecchio graphics card is set to be the company's most powerful processor ever designed, and the chip is indeed looking like an engineering marvel. From Intel's previous teasers, we have learned that Ponte Vecchio is built using 47 "magical tiles" or 47 dies which are responsible either for computing elements, Rambo Cache, Xe links, or something else. Today, we are getting a new piece of information coming from Igor's LAB, regarding the Ponte Vecchio and some of its design choices. For starters, the GPU will be a heterogeneous design that consists out of many different nodes. Some parts of the GPU will be manufactured on Intel's 10 nm SuperFin and 7 nm technologies, while others will use TSMC's 7 nm and 5 nm nodes. The smaller and more efficient nodes will probably be used for computing elements. Everything will be held together by Intel's EMIB and Foveros 3D packaging.

Next up, we have information that this massive Intel processor will be accountable for around 600 Watts of heat output, which is a lot to cool. That is why in the leaked renders, we see that Intel envisioned these processors to be liquid-cooled, which would make the cooling much easier and much more efficient compared to air cooling of such a high heat output. Another interesting thing is that the Ponte Vecchio is designed to fit inside OAM (OCP Accelerator Module) form factor, an alternative to the regular PCIe-based accelerators in data centers. OAM is used primarily by hyper scalers like Facebook, Amazon, Google, etc., so we imagine that Intel already knows its customers before the product even hits the market.

AMD Shares New Details on Their 3D V-Cache Tech for Zen 3+

AMD via its official YouTube has shared a video that goes into slightly more detail on their usage of V-Cache on the upcoming Zen 3+ CPUs. Firstly demoed to the public on AMD's Computex 2021 event, the 3D V-Cache leverages TSMC's SoIC stacking technology, which enables silicon developments along the Z axis, instead of the more usual footprint increase along the X axis. The added 3D V-Cache, which was shown in Computex as being deployed in a prototype Ryzen 9 5900X 12-core CPU, adds 64 MB of L3 cache to each CCX (the up-to-eight-cores core complex on AMD's latest Zen design), basically tripling the amount of L3 cache available for the CPU. This, in turn, was shown to increase FPS in games quite substantially (somewhere around 15%), as games in particular are sensitive to this type of CPU resources.

The added information explains that there is no usage of microbumps - instead, there is a perfect alignment between the bottom layer (with the CCX) and the top layer (the L3 cache) which enables the bonding process to occur naturally via the TSVs (Through Silicon Vias) already present in the silicon, in a zero-gap manner, between both halves of the CPU-cache sandwich. To enable this, AMD flipped the CCX upside down (the core complex now faces the bottom of the chip, instead of the top), shaved 95% of the silicon on top of the upside-down core complexes, and then attaches the 3D V-Cache chips on top of this formation. This also has the added bonus of decreasing the distance between the L3 cache and the CCX (the distance between both in the Z axis is around 1,000 times smaller than if the L3 cache was deployed in the classical X axis), which decreases power consumption, temperatures, and latency, allowing for further increases to system performance. Look after the break for the full video.

AMD "Milan-X" Processor Could Use Stacked Dies with X3D Packaging Technology

AMD is in a constant process of processor development, and there are always new technologies on the horizon. Back in March of 2020, the company has revealed that it is working on new X3D packaging technology, that integrated both 2.5D and 3D approaches to packing semiconductor dies together as tightly as possible. Today, we are finally getting some more information about the X3D technology, as we have the first codename of the processor that is featuring this advanced packaging technology. According to David Schor, we have learned that AMD is working on a CPU that uses X3D tech with stacked dies, and it is called Milan-X.

The Milan-X CPU is AMD's upcoming product designed for data center usage. The rumors suggest that the CPU is designed for heavy bandwidth and presumably a lot of computing power. According to ExecutableFix, the CPU uses a Genesis-IO die to power the connectivity, which is an IO die from EPYC Zen 3 processors. While this solution is in the works, we don't know the exact launch date of the processor. However, we could hear more about it in AMD's virtual keynote at Computex 2021. For now, take this rumor with a grain of salt.
AMD X3D Packaging Technology

SK Hynix Envisions the Future: 600-Layer 3D NAND and EUV-made DRAM

On March 22nd, the CEO of SK Hynix, Seok-Hee Lee, gave a keynote speech to the IEEE International Reliability Physics Symposium (IRPS) and shared with experts a part of its plan for the future of SK Hynix products. The CEO took the stage and delivered some conceptual technologies that the company is working on right now. At the center of the show, two distinct products stood out - 3D NAND and DRAM. So far, the company has believed that its 3D NAND scaling was very limited and that it can push up to 500 layers sometime in the future before the limit is reached. However, according to the latest research, SK Hynix will be able to produce 600-layer 3D NAND technology in the distant future.

So far, the company has managed to manufacture and sample 512Gb 176-layer 3D NAND chips, so the 600-layer solutions are still far away. Nonetheless, it is a possibility that we are looking at. Before we reach that layer number, there are various problems needed to be solved so the technology can work. According to SK Hynix, "the company introduced the atomic layer deposition (ALD) technology to further improve the cell property of efficiently storing electric charges and exporting them when needed, while developing technology to maintain uniform electric charges over a certain amount through the innovation of dielectric materials. In addition to this, to solve film stress issues, the mechanical stress levels of films is controlled and the cell oxide-nitride (ON) material is being optimized. To deal with the interference phenomenon between cells and charge loss that occur when more cells are stacked at a limited height, SK Hynix developed the isolated-charge trap nitride (isolated-CTN) structure to enhance reliability."

ADATA Explains Changes with XPG SX8200 Pro SSD

ADATA has recently been in a spot of controversy when it comes to their XPG SX8200 Pro solid-state drive (SSD). The company has reportedly shipped many different configurations of the SSD with different drive controller clock speeds and different NAND flash. According to the original report, ADATA has first shipped the SX8200 Pro SSD with Silicon Motion SM2262ENG SSD controller, running at 650 MHz with IMFT 64-layer TLC NAND Flash. However, it was later reported that the SSD was updated to use the Silicon Motion SM2262G SSD controller, clocked at 575 MHz. With this report, many users have gotten concerned and started to question the company's practices. However, ADATA later ensured everyone that performance is within the specifications and there is no need to worry.

Today, we have another report about the ADATA XPG SX8200 Pro SSD. According to a Redditor, ADATA has once again updated its SSD with a different kind of NAND Flash, however, this time the report indicated that performance was impacted. Tom's Hardware has made a table of changes showing as many as five revisions of the SSD, all with different configurations of SSD controllers and NAND Flash memory. We have contacted ADATA to clarify the issues that have emerged, and this is the official response that the company gave us.

Kioxia and Western Digital Announce 6th-Generation 162-layer 3D NAND Flash Memory

Kioxia Corporation and Western Digital Corp., today announced that the companies have developed their sixth-generation, 162-layer 3D flash memory technology. Marking the next milestone in the companies' 20-year joint-venture partnership, this is the companies' highest density and most advanced 3D flash memory technology to date, utilizing a wide range of technology and manufacturing innovations.

"Through our strong partnership that has spanned two decades, Kioxia and Western Digital have successfully created unrivaled capabilities in manufacturing and R&D," said Masaki Momodomi, Chief Technology Officer, Kioxia. "Together, we produce over 30 percent of the world's flash memory bits and are steadfast in our mission to provide exceptional capacity, performance and reliability at a compelling cost. We each deliver this value proposition across a range of data-centric applications from personal electronics to data centers as well as emerging applications enabled by 5G networks, artificial intelligence and autonomous systems."

TSMC Partners With Google and AMD to Push 3D Silicon

Silicon manufacturing is starting to get harder and harder every day, with new challenges appearing daily. It requires massive investment and massive knowledge to keep a silicon manufacturing company afloat. No company can survive that alone, so some collaborations are emerging. Today, thanks to the sources of Nikkei Asia, we have information that Taiwanese Semiconductor Manufacturing Company (TSMC) is collaborating with Google to push the production of 3D chip manufacturing process, that is said to overcome some of the silicon manufacturing difficulties. The sources also say that AMD is involved in the process as well, making Google and AMD the first customers of the advanced 3D chip design. The two companies are preparing designs for the new way of creating silicon and will help TSMC test and certify the process.

TSMC will deploy the 3D silicon manufacturing technology at its chip packaging plant in Miaoli, which is supposed to do mass production in 2022. With Google and AMD being the first customers of new 3D technology, it is exciting to see what new products will look like and how they will perform. The 3D approach is said to bring huge computing power increase, however, it is a waiting game now to see how it will look like.

Basemark Launches GPUScore Relic of Life RayTracing Benchmark

Basemark is pioneer in GPU benchmarking. Our current product Basemark GPU has been improving the 3D graphics industry since 2016. After releasing GPU 1.2 in March Basemark development team has been really busy developing brand new benchmark - GPUScore. GPUScore benchmark will introduce hyper realistic, true gaming type of content in three different workloads: Relic of Life, Sacret Path and Expedition.

GPUScore Relic of Life is targeted to benchmark high end graphics cards. It is completely new benchmark with many new features. The key new feature is real-time ray traced reflections and reflections of reflections. The benchmark will not only support Windows & DirectX 12, but also Linux & Vulkan raytracing.

AMD Graphics Drivers Have a CreateAllocation Security Vulnerability

Discovering vulnerabilities in software is not an easy thing to do. There are many use cases and states that need to be tested to see a possible vulnerability. Still, security researchers know how to find those and they usually report it to the company that made the software. Today, AMD has disclosed that there is a vulnerability present in the company graphics driver powering the GPUs and making them work on systems. Called CreateAllocation (CVE-2020-12911), the vulnerability is marked with a score of 7.1 in the CVSSv3 test results, meaning that it is not a top priority, however, it still represents a big problem.

"A denial-of-service vulnerability exists in the D3DKMTCreateAllocation handler functionality of AMD ATIKMDAG.SYS 26.20.15029.27017. A specially crafted D3DKMTCreateAllocation API request can cause an out-of-bounds read and denial of service (BSOD). This vulnerability can be triggered from a guest account, " says the report about the vulnerability. AMD states that a temporary fix is implemented by simply restarting your computer if a BSOD happens. The company also declares that "confidential information and long-term system functionality are not impacted". AMD plans to release a fix for this software problem sometime in 2021 with the new driver release. You can read more about it here.

TSMC Begins Construction of 2 nm Manufacturing Facility

TSMC, the leading semiconductor foundry in the world, has reportedly begun construction of its 2 nm manufacturing facility. According to a DigiTimes report, translated by @chiakokhua on Twitter, besides the construction of 2 nm R&D center, TSMC has also started the construction of the manufacturing facility for that node, so it will be ready in time. Please do note that the node name doesn't represent the size of the transistor, so it will not actually be 2 nm wide. The new facilities will be located near TSMC's headquarters in Hsinchu Science Park, Taiwan. The report also confirms the first details about the node, specifically that it will use Gate-All-Around (GAA) technology. And there is also another interesting piece of information regarding even smaller node, the planning for 1 nm node has begun according to the source.

Besides advanced nodes, TSMC also laid out clear plans to accelerate the push of advanced packaging technology. That includes SoIC, InFO, CoWoS, and WoW. All of these technologies are classified as "3D Fabric" by the company, even though some are 2.5D. These technologies will be mass-produced at "ZhuNan" and "NanKe" facilities starting in the second half of 2021, and are expected to significantly contribute to the company's profits. It is also reported that the competing foundry, Samsung, has a 3D packaging technology of its own called X-cube, however, it is attracting customers a lot slower than TSMC due to the high costs of the new technology.

Rambus Advances HBM2E Performance to 4.0 Gbps for AI/ML Training Applications

Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it has achieved a record 4 Gbps performance with the Rambus HBM2E memory interface solution consisting of a fully-integrated PHY and controller. Paired with the industry's fastest HBM2E DRAM from SK hynix operating at 3.6 Gbps, the solution can deliver 460 GB/s of bandwidth from a single HBM2E device. This performance meets the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI/ML training and high-performance computing (HPC) applications.

"With this achievement by Rambus, designers of AI and HPC systems can now implement systems using the world's fastest HBM2E DRAM running at 3.6 Gbps from SK hynix," said Uksong Kang, vice president of product planning at SK hynix. "In July, we announced full-scale mass-production of HBM2E for state-of-the-art computing applications demanding the highest bandwidth available."

COVID-19 Drives Rise in Global Fab Equipment Spending, SEMI Reports

Soaring pandemic-inspired demand for chips that power everything from communications and IT infrastructures to personal computing, gaming and healthcare electronics will drive an 8% increase in global fab equipment spending in 2020 and a 13% increase in 2021, SEMI announced today in its World Fab Forecast report. Rising demand for semiconductors for datacenter infrastructures and server storage along with the buildup of safety stock as U.S.-China trade tensions intensify are also contributing to this year's growth.

The bullish trend for overall fab equipment investments comes as the semiconductor industry recovers from a 9% decline in fab spending in 2019 and navigates a roller-coaster 2020 with actual and projected spending drops in the first and third quarters mixed with second- and fourth-quarter increases. See figure below:

AMD Preparing Additional Ryzen 4000G Renoir series SKUs, Ryzen 7 Pro 4750G Benchmarked

AMD Ryzen 4000 series of desktop APUs are set to be released next month as a quiet launch. What we expected to see is a launch covering only a few models ranging from Ryzen 3 to Ryzen 7 level, meaning that there would be configurations equipped with anything from 4C/8T to 8C/16T. In the beginning thanks to all the leaks we expected to see six models (listed in the table below), however thanks to discovery, we could be looking at even more SKUs of the Renoir family of APUs. Mentioned in the table are some new entries to both consumer and pro-grade users which means AMD will probably do a launch of both editions, possibly on the same day. We are not sure if that is the case, however, it is just a speculation.
AMD Ryzen 4000G Renoir SKUs

Micron Delivers Client NVMe Performance and Value SSDs With Industry-Leading Capacity Sizes and QLC NAND

Micron Technology, Inc., today announced new client solid-state drives (SSDs) that bring NVMe performance to client computing applications, freeing laptops, workstations and other portables from legacy architectures that can rob devices of battery power, performance and productivity. The Micron 2300 SSD combines the power and density needed to drive compute-heavy applications in a compact form factor with the reduced power consumption modern mobile users demand. For the first time, Micron brings together NVMe performance and low-cost quad-level-cell (QLC) NAND in the Micron 2210 QLC SSD. It combines fast NVMe throughput and Micron's leadership in QLC technology to offer flash capabilities at hard disk drive-like price points while reducing power consumption by 15 times when compared to hard drives.
Micron 2300 NVMe SSD

Intel's Alder Lake Processors Could use Foveros 3D Stacking and Feature 16 Cores

Intel is preparing lots of interesting designs for the future and it is slowly shaping their vision for the next generation of computing devices. Following the big.LITTLE design principle of Arm, Intel decided to try and build its version using x86-64 cores instead of Arm ones, called Lakefield. And we already have some information about the new Alder Lake CPUs based on Lakefield design that are set to be released in the future. Thanks to a report from Chrome Unboxed, who found the patches submitted to Chromium open-source browser, used as a base for many browsers like Google Chrome and new Microsoft Edge, there is a piece of potential information that suggests Alder Lake CPUs could arrive very soon.

Rumored to feature up to 16 cores, Alder Lake CPUs could present an x86 iteration of the big.LITTLE design, where one pairs eight "big" and eight "small" cores that are activated according to increased or decreased performance requirements, thus bringing the best of both worlds - power efficiency and performance. This design would be present on Intel's 3D packaging technology called Foveros. The Alder Lake CPU support patch was added on April 27th to the Chrome OS repository, which would indicate that Intel will be pushing these CPUs out relatively quickly. The commit message titled "add support for ADL gpiochip" contained the following: "On Alderlake platform, the pinctrl (gpiochip) driver label is "INTC105x:00", hence declare it properly." The Chrome Unboxed speculates that Alder Lake could come out in mid or late 2021, depending on how fast Intel could supply OEMs with enough volume.
Intel Lakefield

BenQ Launches SW321C 32-inch Monitor

BenQ today announced the latest addition to its monitor family design for professional use. The SW321C, as it is called, is a 32-inch monitor with an IPS panel of 4K (3840×2160p) resolution. The panel itself is a 60 Hz screen with 250 nits of brightness, 1000:1 contrast ratio, 5 ms GtG response time, and it offers 178-degree viewing angles, which is standard for IPS panels. When it comes to the color coverage and the ability to accurately represent them, the SW321C features 95% of the DCI-P3, 99% of the Adobe RGB, and 100% of the sRGB color gamut. It has a 16-bit 3D look-up table (LUT) and features calibration for DeltaE ≤ 2.

The monitor comes with HDR10 specification, however, due to the brightness of 250 nits, it is not capable of performing any serious HDR content editing. Another interesting note is that this monitor supports Hybrid Log-Gamma (HLG) standard, which is an uncommon one. For input, the monitor had support for one DisplayPort 1.4, two HDMI 2.0, and one USB-C port. There is a dual-port USB hub, which has an SD card reader right next to it, making this very useful feature for photographers. Exact pricing and availability of this monitor are unknown, however, it is supposed to hit the market soon.
BenQ SW321C monitor BenQ SW321C monitor BenQ SW321C monitor

Intel and Micron Sign New Agreement for 3D XPoint Shipment

Intel and Micron have signed a new agreement for the production of 3D XPoint memory. As currently the only source of 3D XPoint memory solutions, Micron will get a significant increase in cash flow coming from Intel for the memory production. While Intel and Micron ended their partnership on 3D XPoint memory, they have signed a new contract for the production and supply of new 3D XPoint wafers to Intel. This shows that the demand for 3D XPoint memory is strong, so Intel needs production capacity to deliver the memory, and Micron is the obvious choice.

Previously, Intel sold its ownership of Lehi fab based in Utah, which was manufacturing the 3D XPoint memory solutions, so it was left to Micron to use. However, they signed a new deal and now Micron is in charge of manufacturing and addressing the supply issues for Intel's future Optane products. The new agreement comes with changed pricing and forecast of the sales, so Intel is likely paying more cash to Micron this time.
Intel 3D XPoint

TSMC and Broadcom Enhance the CoWoS Platform with World's First 2X Reticle Size Interposer

TSMC today announced it has collaborated with Broadcom on enhancing the Chip-on-Wafer-on-Substrate (CoWoS ) platform to support the industry's first and largest 2X reticle size interposer. With an area of approximately 1,700mm2, this next generation CoWoS interposer technology significantly boosts computing power for advanced HPC systems by supporting more SoCs as well as being ready to support TSMC's next-generation five-nanometer (N5) process technology.

This new generation CoWoS technology can accommodate multiple logic system-on-chip (SoC) dies, and up to 6 cubes of high-bandwidth memory (HBM), offering as much as 96 GB of memory. It also provides bandwidth of up to 2.7 terabytes per second, 2.7 times faster than TSMC's previously offered CoWoS solution in 2016. With higher memory capacity and bandwidth, this CoWoS solution is well-suited for memory-intensive workloads such as deep learning, as well as workloads for 5G networking, power-efficient datacenters, and more. In addition to offering additional area to increase compute, I/O, and HBM integration, this enhanced CoWoS technology provides greater design flexibility and yield for complex ASIC designs in advanced process nodes.
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