News Posts matching #7 nm EUV

Return to Keyword Browsing

Intel Scraps 10nm for Desktop, Brazen it Out with 14nm Skylake Till 2022?

In a shocking piece of news, Intel has reportedly scrapped plans to launch its 10 nm "Ice Lake" microarchitecture on the client desktop platform. The company will confine its 10 nm microarchitectures, "Ice Lake" and "Tiger Lake" to only the mobile platform, while the desktop platform will see derivatives of "Skylake" hold Intel's fort under the year 2022! Intel gambles that with HyperThreading enabled across the board and increased clock-speeds, it can restore competitiveness with AMD's 7 nm "Zen 2" Ryzen processors with its "Comet Lake" silicon that offers core-counts of up to 10.

"Comet Lake" will be succeeded in 2021 by the 14 nm "Rocket Lake" silicon, which somehow combines a Gen12 iGPU with "Skylake" derived CPU cores, and possibly increased core-counts and clock speeds over "Comet Lake." It's only 2022 that Intel will ship out a truly new microarchitecture on the desktop platform, with "Meteor Lake." This chip will be built on Intel's swanky 7 nm EUV silicon fabrication node, and possibly integrate CPU cores more advanced than even "Willow Cove," possibly "Golden Cove."

Intel's Gargantuan Next-gen Enterprise CPU Socket is LGA4677

Intel has finalized design of its next-generation Xeon Scalable enterprise CPU socket for its "Sapphire Rapids" processors. Called LGA4677, the socket succeeds LGA3647, and is bound for a 2021 market release. Intel will have transitioned to its advanced 7 nm EUV silicon fabrication node on the CPU front, and has adopted an "enterprise-first" strategy for the node. LGA4677 will be designed to handle the extremely high bandwidth of PCI-Express Gen 5, which doubles bandwidth over PCIe gen 4.0, and adds several enterprise-specific features Intel is rolling out in advance as part of its CXL interconnect. These details, along with a prototype LGA4189 socket, was revealed at an exhibit by TE Connectivity, a company that manufactures the socket. The additional pin-count could enable Intel to not just deploy PCI-Express Gen 5, but also expand I/O in other directions, such as more memory channels, dedicated Persistent Memory I/O, etc.

AMD Zen 3 Could Bid the CCX Farewell, Feature Updated SMT

With its next-generation "Zen 3" CPU microarchitecture designed for the 7 nm EUV silicon fabrication process, AMD could bid the "Zen" compute complex or CCX farewell, heralding chiplets with monolithic last-level caches (L3 caches) that are shared across all cores on the chiplet. AMD embraced a quad-core compute complex approach to building multi-core processors with "Zen." At the time, the 8-core "Zeppelin" die featured two CCX with four cores, each. With "Zen 2," AMD reduced the CPU chiplet to only containing CPU cores, L3 cache, and an Infinity Fabric interface, talking to an I/O controller die elsewhere on the processor package. This reduces the economic or technical utility in retaining the CCX topology, which limits the amount of L3 cache individual cores can access.

This and more juicy details about "Zen 3" were put out by a leaked (later deleted) technical presentation by company CTO Mark Papermaster. On the EPYC side of things, AMD's design efforts will be spearheaded by the "Milan" multi-chip module, featuring up to 64 cores spread across eight 8-core chiplets. Papermaster talked about how the individual chiplets will feature "unified" 32 MB of last-level cache, which means a deprecation of the CCX topology. He also detailed an updated SMT implementation that doubles the number of logical processors per physical core. The I/O interface of "Milan" will retain PCI-Express gen 4.0 and eight-channel DDR4 memory interface.

AMD Readies the Low-Power "Dali" APU for Thin-and-Light Notebooks

AMD is expected to bring back its low-power APU family in 2020 with the new "Dali" silicon. Updated company roadmap slides see the inclusion of "Dali" as a "value mobile APU," positioned under "Renoir," a performance APU targeting both the mainstream notebook and desktop (socket AM4) platforms. AMD looks keen to branch out its APU business in two directions.

"Renoir" is expected to be a "Zen 2" based APU with CPU performance matching at least the Ryzen 5 3600 or 3700X, and a faster "Vega" based iGPU. It wouldn't surprise us if "Dali" is a monolithic 7 nm die with two "Zen 2" CPU cores and a tiny iGPU with 3-4 compute units. "Renoir," on the other hand, could be an MCM with an 8-core "Zen 2" chiplet and an enlarged I/O controller die that has the iGPU. "Dali" could see the light of the day only in 2020, by which time TSMC could substantially increase its 7 nm volumes and clear the decks for its new 7 nm EUV mass-production.

Intel Switches Gears to 7nm Post 10nm, First Node Live in 2021

Intel's semiconductor manufacturing business has had a terrible past 5 years as it struggled to execute its 10 nanometer roadmap forcing the company's processor designers to re-hash the "Skylake" microarchitecture for 5 generations of Core processors, including the upcoming "Comet Lake." Its truly next-generation microarchitecture, codenamed "Ice Lake," which features a new CPU core design called "Sunny Cove," comes out toward the end of 2019, with desktop rollouts expected 2020. It turns out that the 10 nm process it's designed for, will have a rather short reign at Intel's fabs. Speaking at an investor's summit on Wednesday, Intel put out its silicon fabrication roadmap that sees an accelerated roll-out of Intel's own 7 nm process.

When it goes live and fit for mass production some time in 2021, Intel's 7 nm process will be a staggering 3 years behind TSMC, which fired up its 7 nm node in 2018. AMD is already mass-producing CPUs and GPUs on this node. Unlike TSMC, Intel will implement EUV (extreme ultraviolet) lithography straightaway. TSMC began 7 nm with DUV (deep ultraviolet) in 2018, and its EUV node went live in March. Samsung's 7 nm EUV node went up last October. Intel's roadmap doesn't show a leap from its current 10 nm node to 7 nm EUV, though. Intel will refine the 10 nm node to squeeze out energy-efficiency, with a refreshed 10 nm+ node that goes live some time in 2020.

China-based SMIC to Start Manufacture of 14 nm-class Chips in 2H 2019

As R&D costs for new, smaller manufacturing nodes grow at unprecedented rates across the industry, a new player is set to enter the 14 nm process manufacture competition: China-based SMIC (Semiconductor Manufacturing International Corporation). The company is looking to throw its hat on the lucrative 14 nm process, filling its offerings portfolio under the 28 nm it currently offers as its denser process.

The company expects its 95% yield rate to offer its customers a trusted platform that might help it increase revenue for further investment on its 10 nm and 7 nm EUV nodes, which the company is pursuing (despite other industry veterans, such as former AMD-manufacturing arm GLOBALFOUNDRIES having ceased development on). Manufacturing technology that's competitive with the western world's, and that's developed in-country, is paramount for China's intention of reducing its dependence of foreign technology, which is why this is such a big step for the company and the company's aspirations.

TSMC 7nm EUV Process to Enter Mass-Production in March 2019

TSMC is giving final touches to set its flagship 7 nanometer EUV (extreme ultraviolet lithography) silicon fabrication node at its highest state of readiness for business, called mass-production. At this state, the node can mass-produce products for TSMC's customers. TSMC had taped out its first 7 nm EUV chips in October 2018. The company will also begin risk-production of the more advanced 5 nm node in April, staying on schedule. Mass production of 5 nm chips could commence in the first half of 2020.

The 7 nm EUV node augments TSMC's 7 nm DUV (deep ultraviolet lithography) node that's been already active since April 2018, and producing chips for AMD, Apple, HiSilicon, and Xilinx. At the turn of the year, 7 nm DUV made up 9 percent of TSMC's shipments. With the new node going online, 7 nm (DUV + EUV) could make up 25 percent of TSMC's output by the end of 2019.

NVIDIA to Implement 7nm EUV Node for its 2020 GPUs

NVIDIA will implement the 7 nanometer EUV (extreme ultraviolet) lithography to build its future generation of GPUs slated for 2020, according to Japanese publication MyNavi.jp. The GPU giant could be among the first customers besides IBM, to contract Samsung for 7 nm EUV mass-production of GPUs. IBM will use the Korean semiconductor giant for manufacturing Z-series processors and FPGAs. Samsung announced in October 2018 that it will begin risk-production on its 7 nm EUV node in early-2019.

An earlier report from 2018 also forecast NVIDIA implementing 7 nm DUV (deep ultraviolet) node of TSMC for its 2019 GPU lineup. With news of the company now working with Samsung on 7 nm EUV for 2020, this seems less likely. It's possible that NVIDIA could somehow split its next generation GPU lineup between TSMC 7 nm DUV and Samsung 7 nm EUV, with the latter being used for chips with higher transistor-counts, taking advantage of the node's higher deliverable transistor densities.

IBM Expands Strategic Partnership with Samsung to Include 7nm Chip Manufacturing

IBM today announced an agreement with Samsung to manufacture 7-nanometer (nm) microprocessors for IBM Power Systems , IBM Z and LinuxONE , high-performance computing (HPC) systems, and cloud offerings. The agreement combines Samsung's industry-leading semiconductor manufacturing with IBM's high-performance CPU designs. This combination is being designed to drive unmatched systems performance, including acceleration, memory and I/O bandwidth, encryption and compression speed, as well as system scaling. It positions IBM and Samsung as strategic partners leading the new era of high-performance computing specifically designed for AI.

"At IBM, our first priority is our clients," said John Acocella, Vice President of Enterprise Systems and Technology Development for IBM Systems. "IBM selected Samsung to build our next generation of microprocessors because they share our level of commitment to the performance, reliability, security, and innovation that will position our clients for continued success on the next generation of IBM hardware."

Intel Unveils a Clean-slate CPU Core Architecture Codenamed "Sunny Cove"

Intel today unveiled its first clean-slate CPU core micro-architecture since "Nehalem," codenamed "Sunny Cove." Over the past decade, the 9-odd generations of Core processors were based on incrementally refined descendants of "Nehalem," running all the way down to "Coffee Lake." Intel now wants a clean-slate core design, much like AMD "Zen" is a clean-slate compared to "Stars" or to a large extent even "Bulldozer." This allows Intel to introduce significant gains in IPC (single-thread performance) over the current generation. Intel's IPC growth curve over the past three micro-architectures has remained flat, and only grew single-digit percentages over the generations prior.

It's important to note here, that "Sunny Cove" is the codename for the core design. Intel's earlier codenaming was all-encompassing, covering not just cores, but also uncore, and entire dies. It's up to Intel's future chip-designers to design dies with many of these cores, a future-generation iGPU such as Gen11, and a next-generation uncore that probably integrates PCIe gen 4.0 and DDR5 memory. Intel details "Sunny Cove" as far as mentioning IPC gains, a new ISA (new instruction sets and hardware capabilities, including AVX-512), and improved scalability (ability to increase core-counts without running into latency problems).

Intel 7nm EUV Node Back On Track, 2x Transistor Densities Over 10nm

There could be light at the end of the tunnel for Intel's silicon fabrication business after all, as the company reported that its 7 nanometer silicon fabrication node, which incorporates EUV (extreme ultraviolet) lithography, is on track. The company stressed in its Nasdaq Investors' Conference presentation that its 7 nm EUV process is de-linked from its 10 nm DUV (deep ultraviolet) node, and that there are separate teams working on their development. The 10 nm DUV node is qualitatively online, and is manufacturing small batches of low-power mobile "Cannon Lake" Core processors.

Cannon Lake is an optical shrink of the "Skylake" architecture to the 10 nm node. Currently there's only one SKU based on it, the Core i3-8121U. Intel utilized the electrical gains from the optical shrink to redesign the client-segment architecture's FPU to support the AVX-512 instruction-set (although not as feature-rich as the company's enterprise-segment "Skylake" derivatives). The jump from 10 nm DUV to 7 nm EUV will present a leap in transistor densities, with Intel expecting nothing short of a doubling. 10 nm DUV uses a combination of 193 nm wavelength ultraviolet lasers and multi-patterning to achieve its transistor density gains over 14 nm++. The 7 nm EUV node uses an extremely advanced 135 nm indirect laser, reducing the need for multi-patterning. The same laser coupled with multi-patterning could be Intel's ticket to 5 nm.

TSMC to Tape Out 100 7 nm Chip Designs by 2019

TSMC has become the de facto leader when it comes to manufacturing technology. The company is on the forefront of new process technologies, and provides solutions for some of the biggest players in the industry, like Apple, NVIDIA, Qualcomm, and AMD, just to name a few. This process leadership means that TSMC is being courted by numerous fabless silicon designers so as to produce their silicon chips with the latest process technologies - part of the reason why TSMC has seen increasing revenues and profits forecasts.

By the end of 2018, TSMC will have taped out 50 7 nm designs, and plans to double that number in 2019. And these design wins don't stand solely on the shoulders of TSMC's first 7 nm technology (which should account for 20% of the company's revenue by 2019); the company will also tape-out chips built upon their 7 nm + EUV process, which will begin production in 2019.
Return to Keyword Browsing