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Samsung & Red Hat Announce Collaboration in the Field of Next-Generation Memory Software

Samsung Electronics and Red Hat today announced a broad collaboration on software technologies for next-generation memory solutions. The partnership will focus on the development and validation of open source software for existing and emerging memory and storage products, including NVMe SSDs; CXL memory; computational memory/storage (HBM-PIM, Smart SSDs) and fabrics — in building an expansive ecosystem for closely integrated memory hardware and software. The exponential growth of data driven by AI, AR and the fast-approaching metaverse is bringing disruptive changes to memory designs, requiring more sophisticated software technologies that better link with the latest hardware advancements.

"Samsung and Red Hat will make a concerted effort to define and standardize memory software solutions that embrace evolving server and memory hardware, while building a more robust memory ecosystem," said Yongcheol Bae, Executive Vice President and Head of the Memory Application Engineering Team at Samsung Electronics. "We will invite partners from across the IT industry to join us in expanding the software-hardware memory ecosystem to create greater customer value."

Samsung Electronics Introduces Industry's First 512GB CXL Memory Module

Samsung Electronics, the world leader in advanced memory technology, today announced its development of the industry's first 512-gigabyte (GB) Compute Express Link (CXL) DRAM, taking an important step toward the commercialization of CXL which will enable extremely high memory capacity with low latency in IT systems. Since introducing the industry's first CXL DRAM prototype with a field-programmable gate array (FPGA) controller in May 2021, Samsung has been working closely with data center, enterprise server and chipset companies to develop an improved, customizable CXL device.

The new CXL DRAM is built with an application-specific integrated circuit (ASIC) CXL controller and is the first to pack 512 GB of DDR5 DRAM, featuring four times the memory capacity and one-fifth the system latency over the previous Samsung CXL offering. "CXL DRAM will become a critical turning point for future computing structures by substantially advancing artificial intelligence (AI) and big data services, as we aggressively expand its usage in next-generation memory architectures including software-defined memory (SDM)," said Cheolmin Park, Vice President of Memory Global Sales & Marketing at Samsung Electronics, and Director of the CXL Consortium. "Samsung will continue to collaborate across the industry to develop and standardize CXL memory solutions, while fostering an increasingly solid ecosystem."

Montage Technology Delivers the World's First CXL Memory eXpander Controller

Montage Technology, a leading data processing and interconnect IC design company, today announced that it has delivered the world's first Compute Express Link (CXL ) Memory eXpander Controller (MXC). The device is designed to be used in Add-in Cards (AIC), Backplanes or EDSFF memory modules to enable significant scaling of memory capacity and bandwidth for data-intensive applications such as high-performance computing (HPC) and artificial intelligence (AI). The MXC is a Type 3 CXL DRAM memory controller. The MXC supports and is compliant with both DDR4 & DDR5 JEDEC standards. It is also designed to the CXL 2.0 specification and supports PCIe 5.0 specification speeds. The MXC provides high-bandwidth and low-latency interconnect between the CPU and the CXL-based devices, allowing them to share memory for higher performance, reduced software stack complexity, and lower data center TCO.

Montage Technology's President, Stephen Tai said, "CXL is a key technology that enables innovative ways to do memory expansion and pooling which will play an important role in next-generation server platforms. I'm very excited that Montage is the first company in the industry to successfully deliver the MXC chip, which signals we are making a critical step towards advancing the CXL interconnect technology to the memory market." CXL Consortium's President, Siamak Tavallaei said, "The CXL Consortium is excited to see continued CXL specification adoption to enable technologies and solutions such as the CXL DRAM Memory eXpander Controller." Montage Technology is working closely with industry-leading memory manufacturers to deliver advanced memory products based on the CXL MXC and help develop a robust memory ecosystem around CXL.

Rambus to Acquire Hardent, Accelerating Roadmap for Next-Generation Data Center Solutions

-Rambus Inc., a provider of industry-leading chips and silicon IP making data faster and safer, today announced it has signed an agreement to acquire Hardent, Inc. ("Hardent"), a leading electronic design company. This acquisition augments the world-class team of engineers at Rambus and accelerates the development of CXL processing solutions for next-generation data centers. With 20 years of semiconductor experience, Hardent's world-class silicon design, verification, compression, and Error Correction Code (ECC) expertise provides key resources for the Rambus CXL Memory Interconnect Initiative.

"Driven by the demands of advanced workloads like AI/ML and the move to disaggregated data center architectures, industry momentum for CXL-based solutions continues to grow," said Luc Seraphin, president and CEO of Rambus. "The addition of the highly-skilled Hardent design team brings key resources that will accelerate our roadmap and expand our reach to address customer needs for next-generation data center solutions." "The Rambus culture and track record of technology leadership is an ideal fit for Hardent," said Simon Robin, president and founder of Hardent. "The team is looking forward to joining Rambus and is excited to be part of a global company advancing the future of data center solutions." In addition, Hardent brings complementary IP and services to the Rambus silicon IP portfolio, expanding the customer base and design wins in automotive and consumer electronic applications. The transaction is expected to close in the second calendar quarter of 2022 and will not materially impact results.

Keysight Delivers Single Vendor Validation Solution for Seamless Support of PCIe 5.0 and 6.0

Keysight Technologies, Inc., a leading technology company that delivers advanced design and validation solutions to help accelerate innovation to connect and secure the world, announced an end-to-end PCIe test solution for digital development and senior engineers that enable the simulation, pathfinding, characterization, validation and compliance testing of PCIe designs. The rapid increase of AI (artificial intelligence) related workloads in data centers and edge computing demand new compute designs. Data center system designers are challenged to provide new higher speed devices within reduced design cycles. New PCIe devices will need to keep up with Ethernet network interfaces in data centers and the emergence of CXL (compute express link).

To maintain performance goals and prepare for the PCIe 6.0 move to pulse amplitude modulation 4-level (PAM4), customers need a smooth transition from PCIe 5.0 to 6.0, where the integrity of PCIe measurements are backed by leading-edge tools and comply with PCIe specifications. With shrinking design cycles, end-to-end solutions from simulation to validation through the layers of the stack are required. Keysight provides a comprehensive physical layer test solution, approved by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) to test transmitters and receivers for all generations of the PCIe specification, which is currently supported by the PCI-SIG integrators list. To reflect the increasing time to market pressure for design engineers, Keysight extends the portfolio to cover PCIe protocol, making it the first end-to-end solution from simulation to full stack validation.

Tanzanite Silicon Solutions Demonstrates Industry's First CXL Based Memory Expansion and Memory Pooling Products

Tanzanite Silicon Solutions Inc., the leader in the development of Compute Express Link (CXL) based products, is unveiling its architectural vision and product roadmap with an SoC mapped to FPGA Proof-Of-Concept vehicle demonstrating Memory Expansion and Memory Pooling, with multi-host CXL based connectivity. Explosive demand for memory and compute to meet the needs of emerging applications such as Artificial Intelligence (AI), Machine Learning (ML), blockchain technology, and the metaverse is outpacing monolithic systems. A disaggregated data center design with composable components for CPU, memory, storage, GPU, and XPU is needed to provide flexible and dynamic pooling of resources to meet the varying demands of heterogenous workloads in an optimal and efficient manner.

Tanzanite's visionary TanzanoidTZ architecture and purpose-built design of a "Smart Logic Interface Connector" (SLICTZ) SoC enables independent scaling and sharing of memory and compute in a pool with low latency within and across server racks. The Tanzanite solution provides a highly scalable architecture for exa-scale level memory capacity and compute acceleration, supporting multiple industry standard form-factors, ranging from E1.S, E3.S, memory expansion board, and memory appliance.

Intel Details Ponte Vecchio Accelerator: 63 Tiles, 600 Watt TDP, and Lots of Bandwidth

During the International Solid-State Circuits Conference (ISSCC) 2022, Intel gave us a more significant look at its upcoming Ponte Vecchio HPC accelerator and how it operates. So far, Intel convinced us that the company created Ponte Vecchio out of 47 tiles glued together in one package. However, the ISSCC presentation shows that the accelerator is structured rather interestingly. There are 63 tiles in total, where 16 are reserved for compute, eight are used for RAMBO cache, two are Foveros base tiles, two represent Xe-Link tiles, eight are HBM2E tiles, and EMIB connection takes up 11 tiles. This totals for about 47 tiles. However, an additional 16 thermal tiles used in Ponte Vecchio regulate the massive TDP output of this accelerator.

What is interesting is that Intel gave away details of the RAMBO cache. This novel SRAM technology uses four banks of 3.75 MB groups total of 15 MB per tile. They are connected to the fabric at 1.3 TB/s connection per chip. In contrast, compute tiles are connected at 2.6 TB/s speeds to the chip fabric. With eight RAMBO cache tiles, we get an additional 120 MB SRAM present. The base tile is a 646 mm² die manufactured in Intel 7 semiconductor process and contains 17 layers. It includes a memory controller, the Fully Integrated Voltage Regulators (FIVR), power management, 16-lane PCIe 5.0 connection, and CXL interface. The entire area of Ponte Vecchio is rather impressive, as 47 active tiles take up 2,330 mm², whereas when we include thermal dies, the total area jumps to 3,100 mm². And, of course, the entire package is much larger at 4,844 mm², connected to the system with 4,468 pins.

Intel "Sapphire Rapids" Xeon 4-tile MCM Annotated

Intel Xeon Scalable "Sapphire Rapids" is an upcoming enterprise processor with a CPU core count of up to 60. This core-count is achieved using four dies inter-connected using EMIB. Locuza, who leads social media with logic die annotation, posted one for "Sapphire Rapids," based on a high-resolution die-shot revealed by Intel in its ISSCC 2022 presentation.

Each of the four dies in "Sapphire Rapids" is a fully-fledged multi-core processor in its own right, complete with CPU cores, integrated northbridge, memory and PCIe interfaces, and other platform I/O. What brings four of these together is the use of five EMIB bridges per die. This allows CPU cores of a die to transparantly access the I/O and memory controlled any of the other dies transparently. Logically, "Sapphire Rapids" isn't unlike AMD "Naples," which uses IFOP (Infinity Fabric over package) to inter-connect four 8-core "Zeppelin" dies, but the effort here appears to be to minimize the latency arising from an on-package interconnect, toward a high-bandwidth, low-latency one that uses silicon bridges with high-density microscopic wiring between them (akin to an interposer).

SiPearl Partners With Intel to Deliver Exascale Supercomputer in Europe

SiPearl, the designer of the high computing power and low consumption microprocessor that will be the heart of European supercomputers, has entered into a partnership with Intel in order to offer a common offer dedicated to the first exascale supercomputers in Europe. This partnership will offer their European customers the possibility of combining Rhea, the high computing power and low consumption microprocessor developed by SiPearl, with Intel's Ponte Vecchio accelerator, thus creating a high performance computing node that will promote the deployment of the exascale supercomputing in Europe.

To enable this powerful combination, SiPearl plans to use and optimize for its Rhea microprocessor the open and unified programming interface, oneAPI, created by Intel. Using this single solution across the entire heterogeneous compute node, consisting of Rhea and Ponte Vecchio, will increase developer productivity and application performance.

Samsung Introduces Industry's First Open-source Software Solution for CXL Memory Platform

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, today introduced the first open-source software solution, the Scalable Memory Development Kit (SMDK), that has been specially designed to support the Compute Express Link (CXL) memory platform. In May, Samsung unveiled the industry's first CXL memory expander that allows memory capacity and bandwidth to scale to levels far exceeding what is possible in today's server systems. Now, the company's CXL platform is being extended beyond hardware to offer easy-to-integrate software tools, making CXL memory much more accessible to data center system developers for emerging artificial intelligence (AI), machine learning (ML) and 5G-edge markets.

The CXL interconnect is an open, industry-backed standard that enables different types of devices such as accelerators, memory expanders and smart I/O devices to work more efficiently when processing high-performance computational workloads. "In order for data center and enterprise systems to smoothly run next-generation memory solutions like CXL, development of corresponding software is a necessity," said Cheolmin Park, vice president of the Memory Product Planning Team at Samsung Electronics. "Today, Samsung is reinforcing its commitment toward delivering a total memory solution that encompasses hardware and software, so that IT OEMs can incorporate new technologies into their systems much more effectively."

Penetration Rate of Ice Lake CPUs in Server Market Expected to Surpass 30% by Year's End as x86 Architecture Remains Dominant, Says TrendForce

While the server industry transitions to the latest generation of processors based on the x86 platform, the Intel Ice Lake and AMD Milan CPUs entered mass production earlier this year and were shipped to certain customers, such as North American CSPs and telecommunication companies, at a low volume in 1Q21, according to TrendForce's latest investigations. These processors are expected to begin seeing widespread adoption in the server market in 3Q21. TrendForce believes that Ice Lake represents a step-up in computing performance from the previous generation due to its higher scalability and support for more memory channels. On the other hand, the new normal that emerged in the post-pandemic era is expected to drive clients in the server sector to partially migrate to the Ice Lake platform, whose share in the server market is expected to surpass 30% in 4Q21.

TrendForce: Enterprise SSD Contract Prices Likely to Increase by 15% QoQ for 3Q21 Due to High SSD Demand and Short Supply of Upstream IC Components

The ramp-up of the Intel Ice Lake and AMD Milan processors is expected to not only propel growths in server shipment for two consecutive quarters from 2Q21 to 3Q21, but also drive up the share of high-density products in North American hyperscalers' enterprise SSD purchases, according to TrendForce's latest investigations. In China, procurement activities by domestic hyperscalers Alibaba and ByteDance are expected to increase on a quarterly basis as well. With the labor force gradually returning to physical offices, enterprises are now placing an increasing number of IT equipment orders, including servers, compared to 1H21. Hence, global enterprise SSD procurement capacity is expected to increase by 7% QoQ in 3Q21. Ongoing shortages in foundry capacities, however, have led to the supply of SSD components lagging behind demand. At the same time, enterprise SSD suppliers are aggressively raising the share of large-density products in their offerings in an attempt to optimize their product lines' profitability. Taking account of these factors, TrendForce expects contract prices of enterprise SSDs to undergo a staggering 15% QoQ increase for 3Q21.

Samsung Unveils Industry-First Memory Module Incorporating New CXL Interconnect

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, today unveiled the industry's first memory module supporting the new Compute Express Link (CXL) interconnect standard. Integrated with Samsung's Double Data Rate 5 (DDR5) technology, this CXL-based module will enable server systems to significantly scale memory capacity and bandwidth, accelerating artificial intelligence (AI) and high-performance computing (HPC) workloads in data centers.

The rise of AI and big data has been fueling the trend toward heterogeneous computing, where multiple processors work in parallel to process massive volumes of data. CXL—an open, industry-supported interconnect based on the PCI Express (PCIe) 5.0 interface—enables high-speed, low latency communication between the host processor and devices such as accelerators, memory buffers and smart I/O devices, while expanding memory capacity and bandwidth well beyond what is possible today. Samsung has been collaborating with several data center, server and chipset manufacturers to develop next-generation interface technology since the CXL consortium was formed in 2019.

Intel "Sapphire Rapids" Xeon Processor Could Feature Up To 80 Cores: New Leak

Intel's upcoming Xeon "Sapphire Rapids" enterprise processor come come with CPU core-counts as high as 80, according to the latest round of photo-leaks. An earlier article predicted the chip cram up to 56 cores alongside on-package HBM. The processor reportedly features up to 80 cores, spread across four 20-core chiplets. Unlike on the latest AMD EPYC processor, there doesn't appear to be a centralized I/O controller die. This particular processor is based in the LGA4189 package, which features additional pins compared to the LGA4577-X socket from the 56-core leak. The newer socket has additional pins that enable next-gen I/O, which include PCI-Express Gen 5.0, and CXL 1.1 interface.

Microchip Announces World's First PCI Express 5.0 Switches

Applications such as data analytics, autonomous-driving and medical diagnostics are driving extraordinary demands for machine learning and hyperscale compute infrastructure. To meet these demands, Microchip Technology Inc. today announced the world's first PCI Express (PCIe) 5.0 switch solutions—the Switchtec PFX PCIe 5.0 family—doubling the interconnect performance for dense compute, high speed networking and NVM Express (NVMe ) storage. Together with the XpressConnect retimers, Microchip is the industry's only supplier of both PCIe Gen 5 switches and PCIe Gen 5 retimer products, delivering a complete portfolio of PCIe Gen 5 infrastructure solutions with proven interoperability.

"Accelerators, graphic processing units (GPUs), central processing units (CPUs) and high-speed network adapters continue to drive the need for higher performance PCIe infrastructure. Microchip's introduction of the world's first PCIe 5.0 switch doubles the PCIe Gen 4 interconnect link rates to 32 GT/s to support the most demanding next-generation machine learning platforms," said Andrew Dieckmann, associate vice president of marketing and applications engineering for Microchip's data center solutions business unit. "Coupled with our XpressConnect family of PCIe 5.0 and Compute Express Link (CXL ) 1.1/2.0 retimers, Microchip offers the industry's broadest portfolio of PCIe Gen 5 infrastructure solutions with the lowest latency and end-to-end interoperability."

Intel Xeon "Sapphire Rapids" LGA4677-X Processor Sample Pictured

Here are some of the first pictures of the humongous Intel Xeon "Sapphire Rapids-SP" processor, in the flesh. Pictured by YuuKi-AnS on Chinese micro-blogging site bilibili, the engineering sample looks visibly larger than an AMD EPYC. Bound for 2021, this processor will leverage the latest generation of Intel's 10 nm Enhanced SuperFin silicon fabrication node, the latest I/O that include 8-channel DDR5 memory, a large number of PCI-Express gen 5.0 lanes, and ComputeXpress Link (CXL) interconnect. Perhaps the most interesting bit of information from the YuuKi-AnS has to be the mention of an on-package high-bandwidth memory solution. The processors will introduce an IPC uplift over "Ice Lake-SP" processors, as they use the newer "Willow Cove" CPU cores.

Intel Confirms HBM is Supported on Sapphire Rapids Xeons

Intel has just released its "Architecture Instruction Set Extensions and Future Features Programming Reference" manual, which serves the purpose of providing the developers' information about Intel's upcoming hardware additions which developers can utilize later on. Today, thanks to the @InstLatX64 on Twitter we have information that Intel is bringing on-package High Bandwidth Memory (HBM) solution to its next-generation Sapphire Rapids Xeon processors. Specifically, there are two instructions mentioned: 0220H - HBM command/address parity error and 0221H - HBM data parity error. Both instructions are there to address data errors in HBM so the CPU operates with correct data.

The addition of HBM is just one of the many new technologies Sapphire Rapids brings. The platform is supposedly going to bring many new technologies like an eight-channel DDR5 memory controller enriched with Intel's Data Streaming Accelerator (DSA). To connect to all of the external accelerators, the platform uses PCIe 5.0 protocol paired with CXL 1.1 standard to enable cache coherency in the system. And as a reminder, this would not be the first time we see a server CPU use HBM. Fujitsu has developed an A64FX processor with 48 cores and HBM memory, and it is powering today's most powerful supercomputer - Fugaku. That is showing how much can a processor get improved by adding a faster memory on-board. We are waiting to see how Intel manages to play it out and what we end up seeing on the market when Sapphire Rapids is delivered.

Alleged Intel Sapphire Rapids Xeon Processor Image Leaks, Dual-Die Madness Showcased

Today, thanks to the ServeTheHome forum member "111alan", we have the first pictures of the alleged Intel Sapphire Rapids Xeon processor. Pictured is what appears to be a dual-die design similar to Cascade Lake-SP design with 56 cores and 112 threads that uses two dies. The Sapphire Rapids is a 10 nm SuperFin design that allegedly comes even in the dual-die configuration. To host this processor, the motherboard needs an LGA4677 socket with 4677 pins present. The new LGA socket, along with the new 10 nm Sapphire Rapids Xeon processors are set for delivery in 2021 when Intel is expected to launch its new processors and their respective platforms.

The processor pictured is clearly a dual-die design, meaning that Intel used some of its Multi-Chip Package (MCM) technology that uses EMIB to interconnect the silicon using an active interposer. As a reminder, the new 10 nm Sapphire Rapids platform is supposed to bring many new features like a DDR5 memory controller paired with Intel's Data Streaming Accelerator (DSA); a brand new PCIe 5.0 standard protocol with a 32 GT/s data transfer rate, and a CXL 1.1 support for next-generation accelerators. The exact configuration of this processor is unknown, however, it is an engineering sample with a clock frequency of a modest 2.0 GHz.

CXL Consortium Releases Compute Express Link 2.0 Specification

The CXL Consortium, an industry standards body dedicated to advancing Compute Express Link (CXL) technology, today announced the release of the CXL 2.0 specification. CXL is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. The CXL 2.0 specification adds support for switching for fan-out to connect to more devices; memory pooling for increased memory utilization efficiency and providing memory capacity on demand; and support for persistent memory - all while preserving industry investments by supporting full backwards compatibility with CXL 1.1 and 1.0.

"Datacenter architectures continue to evolve rapidly to support the growing demands of emerging workloads for Artificial Intelligence and Machine Learning, with CXL technology keeping pace to meet the performance and latency demands," said Barry McAuliffe, president, CXL Consortium. "Designed with breakthrough performance and easy adoption as guiding principles, the CXL 2.0 specification is a significant achievement from our dedicated technical work group members."

Arm Announces Next-Generation Neoverse V1 and N2 Cores

Ten years ago, Arm set its sights on deploying its compute-efficient technology in the data center with a vision towards a changing landscape that would require a new approach to infrastructure compute.

That decade-long effort to lay the groundwork for a more efficient infrastructure was realized when we announced Arm Neoverse, a new compute platform that would deliver 30% year-over-year performance improvements through 2021. The unveiling of our first two platforms, Neoverse N1 and E1, was significant and important. Not only because Neoverse N1 shattered our performance target by nearly 2x to deliver 60% more performance when compared to Arm's Cortex-A72 CPU, but because we were beginning to see real demand for more choice and flexibility in this rapidly evolving space.

CXL Consortium and Gen-Z Consortium Announce MOU Agreement

The Compute Express Link (CXL) Consortium and Gen-Z Consortium today announced their execution of a Memorandum of Understanding (MOU), describing a mutual plan for collaboration between the two organizations. The agreement shows the commitment each organization is making to promote interoperability between the technologies, while leveraging and further developing complementary capabilities of each technology.

"CXL technology and Gen-Z are gearing up to make big strides across the device connectivity ecosystem. Each technology brings different yet complementary interconnect capabilities required for high-speed communications," said Jim Pappas, board chair, CXL Consortium. "We are looking forward to collaborating with the Gen-Z Consortium to enable great innovations for the Cloud and IT world."
Motherboard PCB

Xilinx Announces World's Highest Bandwidth, Highest Compute Density Adaptable Platform for Network and Cloud Acceleration

Xilinx, Inc. today announced Versal Premium, the third series in the Versal ACAP portfolio. The Versal Premium series features highly integrated, networked and power-optimized cores and the industry's highest bandwidth and compute density on an adaptable platform. Versal Premium is designed for the highest bandwidth networks operating in thermally and spatially constrained environments, as well as for cloud providers who need scalable, adaptable application acceleration.

Versal is the industry's first adaptive compute acceleration platform (ACAP), a revolutionary new category of heterogeneous compute devices with capabilities that far exceed those of conventional silicon architectures. Developed on TSMC's 7-nanometer process technology, Versal Premium combines software programmability with dynamically configurable hardware acceleration and pre-engineered connectivity and security features to enable a faster time-to-market. The Versal Premium series delivers up to 3X higher throughput compared to current generation FPGAs, with built-in Ethernet, Interlaken, and cryptographic engines that enable fast and secure networks. The series doubles the compute density of currently deployed mainstream FPGAs and provides the adaptability to keep pace with increasingly diverse and evolving cloud and networking workloads.
Xilinx Versal ACAP FPGA

AMD Announces the CDNA and CDNA2 Compute GPU Architectures

AMD at its 2020 Financial Analyst Day event unveiled its upcoming CDNA GPU-based compute accelerator architecture. CDNA will complement the company's graphics-oriented RDNA architecture. While RDNA powers the company's Radeon Pro and Radeon RX client- and enterprise graphics products, CDNA will power compute accelerators such as Radeon Instinct, etc. AMD is having to fork its graphics IP to RDNA and CDNA due to what it described as market-based product differentiation.

Data centers and HPCs using Radeon Instinct accelerators have no use for the GPU's actual graphics rendering capabilities. And so, at a silicon level, AMD is removing the raster graphics hardware, the display and multimedia engines, and other associated components that otherwise take up significant amounts of die area. In their place, AMD is adding fixed-function tensor compute hardware, similar to the tensor cores on certain NVIDIA GPUs.
AMD Datacenter GPU Roadmap CDNA CDNA2 AMD CDNA Architecture AMD Exascale Supercomputer

PCI-Express Gen 6 Reaches Development Milestone, On Track for 2021 Rollout

The PCI-Express gen 6.0 specification reached an important development milestone, with the publication of its version 0.5 first-draft. This provides important pointers to PCI-SIG members on what features and design changes gen 6.0 hopes to bring, and what its all important number is - bandwidth. PCIe gen 6.0 quadruples per-lane bandwidth over gen 4.0 to 64 GT/s (double that of gen 5.0), resulting in bi-directional bandwidth of 256 GB/s in an x16 configuration.

The spec also introduces a new physical layer change, with PAM4 (pulse amplitude modulation) signaling replacing NRZ (non-return to zero), a key ingredient in the generational bandwidth doubling effort. Despite this, PCIe gen 6.0 retains backwards-compatibility with all older generations of PCIe, which could mean the PCIe slot on motherboards may not look any different. PCIe gen 6.0 also introduces FEC (forward error-correction), and has similar per-channel reach as PCIe gen 5.0. Our older article on Intel's proprietary CXL outlines a key feature of PCIe gen 5.0 besides its bandwidth doubling over gen 4.0 - scalability. Although targeting completion in 2021, it could take several more years for the technology to transcend enterprise computing segments and reach the client. PCI-SIG anticipates the need for gen 6.0 kind of bandwidth in the industry by 2025.

7nm Intel Xe GPUs Codenamed "Ponte Vecchio"

Intel's first Xe GPU built on the company's 7 nm silicon fabrication process will be codenamed "Ponte Vecchio," according to a VideoCardz report. These are not gaming GPUs, but rather compute accelerators designed for exascale computing, which leverage the company's CXL (Compute Express Link) interconnect that has bandwidth comparable to PCIe gen 4.0, but with scalability features slated to come out with future generations of PCIe. Intel is preparing its first enterprise compute platform featuring these accelerators codenamed "Project Aurora," in which the company will exert end-to-end control over not just the hardware stack, but also the software.

"Project Aurora" combines up to six "Ponte Vecchio" Xe accelerators with up to two Xeon multi-core processors based on the 7 nm "Sapphire Rapids" microarchitecture, and OneAPI, a unifying API that lets a single kind of machine code address both the CPU and GPU. With Intel owning the x86 machine architecture, it's likely that Xe GPUs will feature, among other things, the ability to process x86 instructions. The API will be able to push scalar workloads to the CPU, and and the GPU's scalar units, and vector workloads to the GPU's vector-optimized SIMD units. Intel's main pitch to the compute market could be significantly lowered software costs from API and machine-code unification between the CPU and GPU.
Image Courtesy: Jan Drewes
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