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AMD Zen 3 Could Bid the CCX Farewell, Feature Updated SMT

With its next-generation "Zen 3" CPU microarchitecture designed for the 7 nm EUV silicon fabrication process, AMD could bid the "Zen" compute complex or CCX farewell, heralding chiplets with monolithic last-level caches (L3 caches) that are shared across all cores on the chiplet. AMD embraced a quad-core compute complex approach to building multi-core processors with "Zen." At the time, the 8-core "Zeppelin" die featured two CCX with four cores, each. With "Zen 2," AMD reduced the CPU chiplet to only containing CPU cores, L3 cache, and an Infinity Fabric interface, talking to an I/O controller die elsewhere on the processor package. This reduces the economic or technical utility in retaining the CCX topology, which limits the amount of L3 cache individual cores can access.

This and more juicy details about "Zen 3" were put out by a leaked (later deleted) technical presentation by company CTO Mark Papermaster. On the EPYC side of things, AMD's design efforts will be spearheaded by the "Milan" multi-chip module, featuring up to 64 cores spread across eight 8-core chiplets. Papermaster talked about how the individual chiplets will feature "unified" 32 MB of last-level cache, which means a deprecation of the CCX topology. He also detailed an updated SMT implementation that doubles the number of logical processors per physical core. The I/O interface of "Milan" will retain PCI-Express gen 4.0 and eight-channel DDR4 memory interface.

AMD Could Release Next Generation EPYC CPUs with Four-Way SMT

AMD has completed design phase of its "Zen 3" architecture and rumors are already appearing about its details. This time, Hardwareluxx has reported that AMD could bake a four-way simultaneous multithreading technology in its Zen 3 core to enable more performance and boost parallel processing power of its data center CPUs. Expected to arrive sometime in 2020, Zen 3 server CPUs, codenamed "MILAN", are expected to bring many architectural improvements and make use of TSMC's 7nm+ Extreme Ultra Violet lithography that brings as much as 20% increase in transistor density.

Perhaps the biggest change we could see is the addition of four-way SMT that should allow a CPU to have four virtual threads per core that will improve parallel processing power and enable data center users to run more virtual machines than ever before. Four-way SMT will theoretically boost performance by dividing micro-ops into four smaller groups so that each thread could execute part of the operation, thus making the execution time much shorter. This being only one application of four-way SMT, we can expect AMD to leverage this feature in a way that is most practical and brings the best performance possible.

2nd Gen AMD EPYC Continues Market Momentum with New Customers

At the European launch in Rome, Italy AMD today highlighted the growing adoption of 2nd Gen AMD EPYC processors across cloud, enterprise and HPC customers. "Today, we are proud to have new platforms from Dell and new customers adopting 2nd Gen AMD EPYC for cloud, enterprise computing and HPC," said Forrest Norrod, senior vice president and general manager, Datacenter and Embedded Solutions Business Group. "We continue to take the AMD EPYC processor to new heights and are thrilled to have the ecosystem supporting us across hardware, software and cloud providers as we face the challenges of the modern data center head-on."

AMD also announced a new addition to the 2nd Generation AMD EPYC family, the AMD EPYC 7H12 processor. The 64 core/128 thread, 2.60 GHz base frequency, 3.30 GHz max boost frequency, 280 W TDP processor is specifically built for HPC customers and workloads, using liquid cooling to deliver leadership supercomputing performance. In an ATOS testing on their BullSequana XH2000, the new AMD EPYC 7H12 processor achieved a LINPACK score of ~ 4.2 TeraFLOPS, ~11% better than the AMD EPYC 7742 processor.

AMD Readies Three HEDT Chipsets: TRX40, TRX80, and WRX80

AMD is preparing to surprise Intel with its 3rd generation Ryzen Threadripper processors derived from the "Rome" MCM (codenamed "Castle Peak" for the client-platform), that features up to 64 CPU cores, a monolithic 8-channel DDR4 memory interface, and 128 PCIe gen 4.0 lanes. For the HEDT platform, AMD could reconfigure the I/O controller die for two distinct sub-platforms within HEDT - one targeting gamers/enthusiasts, and another targeting the demographic that buys Xeon W processors, including the W-3175X. The gamer/enthusiast-targeted processor line could feature a monolithic 4-channel DDR4 memory interface, and 64 PCI-Express gen 4.0 lanes from the processor socket, and additional lanes from the chipset; while the workstation-targeted processor line could essentially be EPYCs, with a wider memory bus width and more platform PCIe lanes; while retaining drop-in backwards-compatibility with AMD X399 (at the cost of physically narrower memory and PCIe I/O).

To support this diverse line of processors, AMD is coming up with not one, but three new chipsets: TRX40, TRX80, and WRX80. The TRX40 could have a lighter I/O feature-set (similar to the X570), and probably 4-channel memory on the motherboards. The TRX80 and WRX80 could leverage the full I/O of the "Rome" MCM, with 8-channel memory and more than 64 PCIe lanes. We're not sure what differentiates the TRX80 and WRX80, but we believe motherboards based on the latter will resemble proper workstation boards in form-factors such as SSI, and be made by enterprise motherboard manufacturers such as TYAN. The chipsets made their way to the USB-IF for certification, and were sniffed out by momomo_us. ASUS is ready with its first motherboards based on the TRX40, the Prime TRX40-Pro, and the ROG Strix TRX40-E Gaming.

GIGABYTE Smashes 11 World Records with New AMD EPYC 7002 Processors

GIGABYTE, a leading server systems builder which recently released a total of 17 new AMD EPYC 7002 Series "Rome" server platforms simultaneously with AMD's own official launch of their next generation CPU, is proud to announce that our new systems have already broken 11 different SPEC benchmark world records. These new world records have not only been achieved against results from all alternative processor based systems but even against competing vendor solutions using the same 2nd Generation AMD EPYC 7002 Series "Rome" processor platform, illustrating that GIGABYTE's system design and engineering is perfectly optimized to deliver the maximum performance possible from the 2nd Generation AMD EPYC.

AMD "Sharkstooth" Shows Up on Geekbench: Possible Zen 2 Threadripper

AMD is possibly testing its 3rd generation Ryzen Threadripper HEDT processors, with an interesting entry showing up on the Geekbench online database. The entry speaks of an "AMD Sharkstooth" processor with 32 cores and 64 threads, with a nominal clock speed of 3.60 GHz, and the long-form model number "AuthenticAMD Family 23 Model 49 Stepping 0." None of the 2nd generation EPYC processors correspond with these specs, and so we're almost certain this is a client-segment Ryzen Threadripper part.

The prototyping platform, which is a motherboard designed in-house by AMD to test the processor's various components and I/O capabilities, is codenamed "WhiteHavenOC-CP." In this Geekbench submission, the processor is paired with around 128 GB of memory, and tested on 64-bit Linux. The platform yields a multi-threaded score of 94,772 points, which is about 18.5 percent higher than what a Ryzen Threadripper 2990WX typically manages when tested on Linux. It is also within 5% of what the Xeon W-3175X manages (around 99,000 points). The production model could be clocked higher. AMD will also use the opportunity to launch a new motherboard chipset while maintaining backwards-compatibility with the AMD X399. This new chipset will enable PCI-Express gen 4.0 and come with stiffer CPU VRM and memory/PCIe wiring specifications to enable higher memory clocks and PCIe link stability. AMD is expected to launch its 3rd gen Ryzen Threadripper this October, to preempt Intel's next HEDT processor series.

Samsung PM1733 SSD and High-Density DIMMs Support AMD EPYC 7002 Series Processors

Samsung Electronics, Ltd., has taken its leadership position in the memory market a step further today by announcing support of the Samsung PM1733 PCIe Gen4 Solid State Drive (SSD) and high density RDIMM and LRDIMM dynamic random access memory (DRAM) for the AMD EPYC 7002 Generation Processors. AMD launched the 2nd Gen AMD EPYC processor in San Francisco yesterday.

"AMD has listened to the needs of its customers in developing the 2nd Gen AMD EPYC processors and has worked closely with us to integrate the best of our cutting-edge memory and storage products," said Jinman Han, senior VP of Memory Product Planning, Samsung Electronics. "With these new datacenter processors, AMD is providing customers with a processor that enables a new standard for the modern datacenter."

SK Hynix Named as Memory & Storage Solutions Partner to Support Latest AMD EPYC 7002 Series

SK Hynix Inc. announced today that its DRAM and Enterprise SSD (eSSD) solutions, including the up-to-date 1Y nm 8 Gb DDR4 DRAM, have been fully tested and validated with the new AMD EPYC 7002 Generation Processors, which were unveiled during AMD's launch event on August 7. The Company has worked closely with AMD to provide memory solutions fully compatible with the 2nd Gen AMD EPYC Processors, targeting high performance data centers.

The SK Hynix DDR4 DRAM supports the maximum speed of 3200 Mbps of the 2nd Gen EPYC Processors[i], which will increase memory performance more than 20% compared to the 1st Gen AMD EPYC Processors. The Company's various DDR4 DRAM solutions, based on the 1Xnm and 1Y nm technology with density of 8 Gb and 16 Gb, have been fully tested and validated with the 2nd Gen EPYC Processors. SK Hynix provides high-density DIMMs with density over 64 GB to support up to 64 cores per socket in the 2nd Gen EPYC.

SK Hynix also provides a full line-up of SATA and PCIe from 480 GB to 8 TB, which have also been validated and tested with the 2nd Gen EPYC. SK Hynix's eSSD solutions are optimized for the latest data center's read-intensive and mixed workload environment.

2nd Gen AMD EPYC Processors Set New Standard for the Modern Datacenter

At a launch event today, AMD was joined by an expansive ecosystem of datacenter partners and customers to introduce the 2nd Generation AMD EPYC family of processors that deliver performance leadership across a broad number of enterprise, cloud and high-performance computing (HPC) workloads. 2nd Gen AMD EPYC processors feature up to 64 "Zen 2" cores in leading-edge 7 nm process technology to deliver record-setting performance while helping reduce total cost of ownership (TCO) by up to 50% across numerous workloads. At the event, Google and Twitter announced new 2nd Gen AMD EPYC processor deployments and HPE and Lenovo announced immediate availability of new platforms.

"Today, we set a new standard for the modern datacenter with the launch of our 2nd Gen AMD EPYC processors that deliver record-setting performance and significantly lower total cost of ownership across a broad set of workloads," said Dr. Lisa Su, president and CEO, AMD. "Adoption of our new leadership server processors is accelerating with multiple new enterprise, cloud and HPC customers choosing EPYC processors to meet their most demanding server computing needs."

AMD Zen 2 EPYC "Rome" Launch Event Live Blog

AMD invited TechPowerUp to their launch event and editor's day coverage of Zen 2 EPYC processors based on the 7 nm process. The event was a day-long affair which included product demos and tours, and capped off with an official launch presentation which we are able to share with you live as the event goes on. Zen 2 with the Ryzen 3000-series processors ushered in a lot of excitement, and for good reason too as our own reviews show, but questions remained on how the platform would scale to the other end of the market. We already knew, for example, that AMD secured many contracts based on their first-generation EPYC processors, and no doubt the IPC increase and expected increased core count would cause similar, if not higher, interest here. We also expect to know shortly about the various SKUs and pricing involved, and also if AMD wants to shed more light on the future of the Threadripper processor family. Read below, and continue past the break, for our live coverage.
21:00 UTC: Lisa Su is on the stage at the Palace of Fine Arts events venue in San Francisco to present AMD's latest developments on EPYC for datacenters, using the Zen 2 microarchitecture.

21:10 UTC: AMD focuses not just on delivering a single chip, but it's goal is to deliver a complete solution for the enterprise.

Intel Internal Memo Reveals that even Intel is Impressed by AMD's Progress

Today an article was posted on Intel's internal employee-only portal called "Circuit News". The post, titled "AMD competitive profile: Where we go toe-to-toe, why they are resurgent, which chips of ours beat theirs" goes into detail about the recent history of AMD and how the company achieved its tremendous growth in recent years. Further, Intel talks about where they see the biggest challenges with AMD's new products, and what the company's "secret sauce" is to fight against these improvements.
The full article follows:

Intel "Sapphire Rapids" Brings PCIe Gen 5 and DDR5 to the Data-Center

As if the mother of all ironies, prior to its effective death-sentence dealt by the U.S. Department of Commerce, Huawei's server business developed an ambitious product roadmap for its Fusion Server family, aligning with Intel's enterprise processor roadmap. It describes in great detail the key features of these processors, such as core-counts, platform, and I/O. The "Sapphire Rapids" processor will introduce the biggest I/O advancements in close to a decade, when it releases sometime in 2021.

With an unannounced CPU core-count, the "Sapphire Rapids-SP" processor will introduce DDR5 memory support to the data-center, which aims to double bandwidth and memory capacity over the DDR4 generation. The processor features an 8-channel (512-bit wide) DDR5 memory interface. The second major I/O introduction is PCI-Express gen 5.0, which not only doubles bandwidth over gen 4.0 to 32 Gbps per lane, but also comes with a constellation of data-center-relevant features that Intel is pushing out in advance as part of the CXL Interconnect. CXL and PCIe gen 5 are practically identical.

AMD Takes a Bigger Revenue Hit than Microsoft from Huawei Ban: Goldman Sachs

The trade ban imposed on Chinese tech giant Huawei by the U.S. Department of Commerce, and ratified through an Executive Order by President Donald Trump, is cutting both ways. Not only are U.S. entities banned from importing products and services from Huawei, but also engaging in trade with them (i.e. selling to them). U.S. tech firms stare at a $11 billion revenue loss by early estimates. Wall Street firm Goldman Sachs compiled a list of companies impacted by the ban, and the extent of their revenue loss. It turns out that AMD isn't a small player, and in fact, stands to lose more revenue in absolute terms than even Microsoft. It earns RMB 268 million (USD $38.79 million) from Huawei, compared to Microsoft's RMB 198 million ($28.66 million). Intel's revenue loss is a little over double that of AMD at RMB 589 million ($84 million), despite its market-share dominance.

That's not all, AMD's exposure is higher than that of Intel, since sales to Huawei make up a greater percentage of AMD's revenues than it does Intel's. AMD exports not just client-segment products such as Ryzen processors and Radeon graphics, but possibly also EPYC enterprise processors for Huawei's server and SMB product businesses. NVIDIA is affected to a far lesser extent than Intel, AMD, and Microsoft. Qualcomm-Broadcom take the biggest hit in absolute revenue terms at RMB 3.5 billion ($508 million), even if their exposure isn't the highest. The duo export SoCs and cellular modems to Huawei, both as bare-metal and licenses. Storage hardware makers aren't far behind, with the likes of Micron, Seagate, and Western Digital taking big hits. Micron exports DRAM and SSDs, while Seagate and WDC export hard drives.

AMD Confirms Launch of Next-gen Ryzen, EPYC and Navi for Q3

During AMD's annual shareholder meeting today, AMD president and CEO Dr. Lisa Su confirmed the launch of next-generation AMD Ryzen, EPYC CPUs and Navi GPUs for the third quarter of this year. The expected products are going to be manufactured on TSMC's 7 nm process and will be using new and improved architectures.

Ryzen 3000 series CPUs are rumored to have up to as much as 16 cores in Ryzen 9 SKUs, 12 cores in Ryzen 7 SKUs and 8 cores in Ryzen 5 SKUs. EPYC server CPUs will be available in models up to 64 cores. All of the new CPUs will be using AMD "Zen 2" architecture that will offer better IPC performance and, as rumors suggest for consumer models, are OC beasts. Navi GPUs are the new 7 nm GPUs that are expected to be very competitive both price and performance wise to NVIDIA's Turing series, hopefully integrating new technologies such as dedicated Ray Tracing cores for higher frame rates in Ray Tracing enabled games. No next generation ThreadRipper launch date was mentioned, so we don't yet know when and if that will that land.

AMD Collaborates with US DOE to Deliver the Frontier Supercomputer

The U.S. Department of Energy today announced a contract with Cray Inc. to build the Frontier supercomputer at Oak Ridge National Laboratory, which is anticipated to debut in 2021 as the world's most powerful computer with a performance of greater than 1.5 exaflops.

Scheduled for delivery in 2021, Frontier will accelerate innovation in science and technology and maintain U.S. leadership in high-performance computing and artificial intelligence. The total contract award is valued at more than $600 million for the system and technology development. The system will be based on Cray's new Shasta architecture and Slingshot interconnect and will feature high-performance AMD EPYC CPU and AMD Radeon Instinct GPU technology.

AMD Reports First Quarter 2019 Financial Results- Gross margin expands to 41%, up 5 percentage points year-over-year

AMD today announced revenue for the first quarter of 2019 of $1.27 billion, operating income of $38 million, net income of $16 million and diluted
earnings per share of $0.01. On a non-GAAP(*) basis, operating income was $84 million, net income was $62 million and diluted earnings per share was $0.06.

"We delivered solid first quarter results with significant gross margin expansion as Ryzen and EPYC processor and datacenter GPU revenue more than doubled year-over-year," said Dr. Lisa Su, AMD president and CEO. "We look forward to the upcoming launches of our next-generation 7nm PC, gaming
and datacenter products which we expect to drive further market share gains and financial growth."

Micron Introduces 9300 Series NVMe Enterprise SSDs

Micron Technology, Inc., today unveiled its new series of flagship solid-state drives (SSDs) featuring the NVM Express (NVMe) protocol, bringing industry-leading storage performance at higher capacities to cloud and enterprise computing markets. The Micron 9300 series of NVMe SSDs enables companies with data-intensive applications to access and process data faster, helping reduce response time.

"The introduction of our third generation of NVMe SSDs endorses our tradition of continued innovation for cloud and enterprise markets," said Derek Dicker, corporate vice president and general manager for Micron's Storage Business Unit. "The Micron 9300 is our flagship series of NVMe SSDs, which feature industry-leading sequential write performance and latency, increased capacities, and delivery of a 28% reduction in power over the previous generation."

AMD "Castle Peak," "Rome," and "Matisse" Referenced in Latest AIDA64 Changelog

FinalWire over the past week posted the latest public beta of AIDA64, which adds support for the three key processor product lines based on AMD's "Zen 2" microarchitecture. The "Matisse" multi-chip module, which received extensive coverage over the past few weeks, will be AMD's main derivative of "Zen 2," designed for the client-segment socket AM4 platform, with up to 16 CPU cores, and the initial flagship product featuring 12 cores. "Rome" is AMD's all-important enterprise-segment MCM for the SP3 platform, with up to 64 CPU cores spread across eight 8-core chiplets interfacing a centralized I/O controller die with a monolithic 8-channel memory controller. It so happens that AMD also wants to update its Ryzen Threadripper line of high-end desktop processors, with "Castle Peak."

"Castle Peak" is codename for 3rd generation Ryzen Threadripper and a client-segment derivative of the "Rome" MCM with a reconfigured I/O controller die that has a monolithic 4-channel DDR4 memory interface, and an unspecified number of CPU cores north of 24. This is for backwards compatibility with the existing AMD X399 motherboards. AMD configures core-count by physically changing the number of 8-core chiplets on the MCM, in addition to disabling cores in groups of 2 within the chiplet. The company could scale core counts looking at its competitive environment. The monolithic quad-channel memory interface could significantly improve the chip's memory performance compared to current-generation Threadrippers, particularly the Threadripper WX series chips in which half the CPU cores are memory bandwidth-starved. The AIDA64 update also improves detection of existing Ryzen/EPYC processors with the K17.3 and K17.5 integrated northbridges.

DOWNLOAD: FinalWire AIDA64 Extreme 5.99.4983 beta

AMD President and CEO Dr. Lisa Su to Deliver COMPUTEX 2019 CEO Keynote

Taiwan External Trade Development Council (TAITRA) announced today that the 2019 COMPUTEX International Press Conference will be held with a Keynote by AMD President and CEO Dr. Lisa Su. The 2019 COMPUTEX International Press Conference & CEO Keynote is scheduled for Monday, May 27 at 10:00 AM in Room 201 of the Taipei International Convention Center (TICC) in Taipei, Taiwan with the keynote topic "The Next Generation of High-Performance Computing".

"COMPUTEX, as one of the global leading technology tradeshows, has continued to advance with the times for more than 30 years. This year, for the first time, a keynote speech will be held at the pre-show international press conference," said Mr. Walter Yeh, President & CEO, TAITRA, "Dr. Lisa Su received a special invitation to share insights about the next generation of high-performance computing. We look forward to her participation attracting more companies to participate in COMPUTEX, bringing the latest industry insights, and jointly sharing the infinite possibilities of the technology ecosystem on this global stage."

AMD's CES 2019 Keynote - Stream & Live Blog

CPUs or GPUs? Ryzen 3000 series up to 16 cores or keeping their eight? Support for raytracing? Navi or die-shrunk Vega for consumer graphics? The questions around AMD's plans for 2019 are still very much in the open, but AMD's Lisa Su's impending livestream should field the answers to many of these questions, so be sure to watch the full livestream, happening in just a moment.

You can find the live stream here, at YouTube.

18:33 UTC: Looking forward, Lisa mentioned a few technology names without giving additional details: "... when you're talking about future cores, Zen 2, Zen 3, Zen 4, Zen 5, Navi, we're putting all of these architectures together, in new ways".

18:20 UTC: New Ryzen 3rd generation processors have been teased. The upcoming processors are based on Zen 2, using 7 nanometer technology. AMD showed a live demo of Forza Horizon 4, using Ryzen third generation, paired with Radeon Vega VII, which is running "consistently over 100 FPS at highest details at 1080p resolution". A second demo, using Cinebench, pitted an 8-core/16-thread Ryzen 3rd generation processor against the Intel Core i9-9900K. The Ryzen CPU was "not final frequency, an early sample". Ryzen achieved a score of 2057 using 135 W, while Intel achieved a score of 2040 using 180 W.. things are looking good for Ryzen 3rd generation indeed. Lisa also confirmed that next-gen Ryzen will support PCI-Express 4.0, which doubles the bandwidth per lane over PCI-Express 3.0. Ryzen third generation will run on the same AM4 infrastructure as current Ryzen; all existing users of Ryzen can simply upgrade to the new processors, when they launch in the middle of 2019 (we think Computex).
Ryzen third generation uses a chiplet design. The smaller die on the right contains 8-cores/16-threads using 7 nanometer technology. The larger die on the left is the IO die, which consists of things like the memory controller and PCI-Express connectivity, to shuffle data between the CPU core die and the rest of the system.

AMD 7nm EPYC "Rome" CPUs in Upcoming Finnish Supercomputer, 200,000 Cores Total

During the next year and a half, the Finnish IT Center for Science (CSC) will be purchasing a new supercomputer in two phases. The first phase consists of Atos' air-cooled BullSequana X400 cluster which makes use of Intel's Cascade Lake Xeon processors along with Mellanox HDR InfiniBand for a theoretical performance of 2 petaflops. Meanwhile, system memory per node will range from 96 GB up to 1.5 TB with the entire system receiving a 4.9 PB Lustre parallel file system as well from DDN. Furthermore, a separate partition of phase one will be used for AI research and will feature 320 NVIDIA V100 NVLinked GPUs configured in 4-GPU nodes. It is expected that peak performance will reach 2.5 petaflops. Phase one will be brought online at some point in the summer of 2019.

Where things get interesting is in phase two, which is set for completion during the spring of 2020. Atos' will be building CSC a liquid-cooled HDR-connected BullSequana XH2000 supercomputer that will be configured with 200,000 AMD EPYC "Rome" CPU cores which for the mathematicians out there works out to 3,125 64 core AMD EPYC processors. Of course, all that x86 muscle will require a great deal of system memory, as such, each node will be equipped with 256 GB for good measure. Storage will consist of an 8 PB Lustre parallel file system that is to be provided by DDN. Overall phase two will increase computing capacity by 6.4 petaflops (peak). With deals like this already being signed it would appear AMD's next-generation EPYC processors are shaping up nicely considering Intel had this market cornered for nearly a decade.

AMD Doubles L3 Cache Per CCX with Zen 2 "Rome"

A SiSoft SANDRA results database entry for a 2P AMD "Rome" EPYC machine sheds light on the lower cache hierarchy. Each 64-core EPYC "Rome" processor is made up of eight 7 nm 8-core "Zen 2" CPU chiplets, which converge at a 14 nm I/O controller die, which handles memory and PCIe connectivity of the processor. The result mentions cache hierarchy, with 512 KB dedicated L2 cache per core, and "16 x 16 MB L3." Like CPU-Z, SANDRA has the ability to see L3 cache by arrangement. For the Ryzen 7 2700X, it reads the L3 cache as "2 x 8 MB L3," corresponding to the per-CCX L3 cache amount of 8 MB.

For each 64-core "Rome" processor, there are a total of 8 chiplets. With SANDRA detecting "16 x 16 MB L3" for 64-core "Rome," it becomes highly likely that each of the 8-core chiplets features two 16 MB L3 cache slices, and that its 8 cores are split into two quad-core CCX units with 16 MB L3 cache, each. This doubling in L3 cache per CCX could help the processors cushion data transfers between the chiplet and the I/O die better. This becomes particularly important since the I/O die controls memory with its monolithic 8-channel DDR4 memory controller.

Intel Could Upstage EPYC "Rome" Launch with "Cascade Lake" Before Year-end

Intel is reportedly working tirelessly to launch its "Cascade Lake" Xeon Scalable 48-core enterprise processor before year-end, according to a launch window timeline slide leaked by datacenter hardware provider QCT. The slide suggests a late-Q4 thru Q1-2019 launch timeline for the XCC (extreme core count) version of "Cascade Lake," which packs 48 CPU cores across two dies on an MCM. This launch is part of QCT's "early shipment program," which means select enterprise customers can obtain the hardware in pre-approved quantities. In other words, this is a limited launch, but one that's probably enough to upstage AMD's 7 nm EPYC "Rome" 64-core processor launch.

It's only by late-Q1 thru Q2-2019 that the Xeon "Cascade Lake" family would be substantially launched, including lower core-count variants that are still 2-die MCMs. This aligns to preempt or match AMD's 7 nm EPYC family rollout through 2019. "Cascade Lake" is probably Intel's final enterprise microarchitecture to be built on the 14 nm++ node, and consists of 2-die multi-chip modules that feature 48 cores, and a 12-channel memory interface (6-channel per die); with 88-lane PCIe from the CPU socket. The processor is capable of multi-socket configurations. It will also be Intel's launch platform for substantially launching its Optane Persistent Memory product series.

Stuttgart-based HLRS to Build a Supercomputer with 10,000 64-core Zen 2 Processors

Höchstleistungsrechenzentrum (HLRS, or High-Performance Computing Center), based in Stuttgart Germany, is building a new cluster supercomputer powered by 10,000 AMD Zen 2 "Rome" 64-core processors, making up 640,000 cores. Called "Hawk," the supercomputer will be HLRS' flagship product, and will open its doors to business in 2019. The slide-deck for Hawk makes a fascinating disclosure about the processors it's based on.

Apparently, each of the 64-core "Rome" EPYC processors has a guaranteed clock-speed of 2.35 GHz. This would mean at maximum load (with all cores loaded 100%), the processor can manage to run at 2.35 GHz. This is important, because the supercomputer's advertised throughput is calculated on this basis, and clients draw up SLAs on throughput. The advertised peak throughput for the whole system is 24.06 petaFLOP/s, although the company is yet to put out nominal/guaranteed performance numbers (which it will only after first-hand testing). The system features 665 TB of RAM, and 26,000 TB of storage.

AMD "Zen 2" IPC 29 Percent Higher than "Zen"

AMD reportedly put out its IPC (instructions per clock) performance guidance for its upcoming "Zen 2" micro-architecture in a version of its Next Horizon investor meeting, and the numbers are staggering. The next-generation CPU architecture provides a massive 29 percent IPC uplift over the original "Zen" architecture. While not developed for the enterprise segment, the stopgap "Zen+" architecture brought about 3-5 percent IPC uplifts over "Zen" on the backs of faster on-die caches and improved Precision Boost algorithms. "Zen 2" is being developed for the 7 nm silicon fabrication process, and on the "Rome" MCM, is part of the 8-core chiplets that aren't subdivided into CCX (8 cores per CCX).

According to Expreview, AMD conducted DKERN + RSA test for integer and floating point units, to arrive at a performance index of 4.53, compared to 3.5 of first-generation Zen, which is a 29.4 percent IPC uplift (loosely interchangeable with single-core performance). "Zen 2" goes a step beyond "Zen+," with its designers turning their attention to critical components that contribute significantly toward IPC - the core's front-end, and the number-crunching machinery, FPU. The front-end of "Zen" and "Zen+" cores are believed to be refinements of previous-generation architectures such as "Excavator." Zen 2 gets a brand-new front-end that's better optimized to distribute and collect workloads between the various on-die components of the core. The number-crunching machinery gets bolstered by 256-bit FPUs, and generally wider execution pipelines and windows. These come together yielding the IPC uplift. "Zen 2" will get its first commercial outing with AMD's 2nd generation EPYC "Rome" 64-core enterprise processors.

Update Nov 14: AMD has issued the following statement regarding these claims.
As we demonstrated at our Next Horizon event last week, our next-generation AMD EPYC server processor based on the new 'Zen 2' core delivers significant performance improvements as a result of both architectural advances and 7nm process technology. Some news media interpreted a 'Zen 2' comment in the press release footnotes to be a specific IPC uplift claim. The data in the footnote represented the performance improvement in a microbenchmark for a specific financial services workload which benefits from both integer and floating point performance improvements and is not intended to quantify the IPC increase a user should expect to see across a wide range of applications. We will provide additional details on 'Zen 2' IPC improvements, and more importantly how the combination of our next-generation architecture and advanced 7nm process technology deliver more performance per socket, when the products launch.
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