Here is the first picture of AMD accelerated processing units in the existing FM1 package and future FM2 package on which the next-generation Trinity APU will be based on. Both packages are very similar, follow AMD's favourite yet archaic PGA design. The pins are physically arranged in a mostly similar fashion, though we don't have a pin map at hand. The difference comes with some of the blanked pins in the sub-central portion of the pin array. The FM2 package has 904 pins, compared to 905 on FM1. One pin is blanked, while a pair of blanked pins are arranged further away from the central cutout.

This makes FM1 and FM2 clearly incompatible. Neither will you be able to use today's A-Series APUs in the FM1 package on future socket FM2 motherboards, nor will you be able to run future FM2 APUs on today's FM1 motherboards. Yet, AMD will port the A75 FCH chipset to the next-generation "Virgo" platform. The FCH or Fusion Controller Hub, like Intel's PCH (Platform Controller Hub), is not much more than a glorified southbridge, and is portable between Fusion platforms as it's essentially a PCI-Express 2.0 x4 device. In the picture below, "Llano" FM1 APU is on the left, and "Trinity" FM2 on the right.

AMD detailed its upcoming "Virgo" PC platform that consists of next-generation "Trinity" APU (accelerated processing unit), and current-generation AMD A75 "Hudson-D" chipset. A notable revelation here is that the next-gen APUs will be compatible with AMD A75, although it will be designed for a new socket called FM2. It remains to be seen if FM1 and FM2 are pin-compatible.

"Trinity" packs four x86-64 cores based on the next-generation "Piledriver" architecture, arranged in two Piledriver modules. A module is a closely-knit group of two cores, with certain shared and dedicated resources. Each Piledriver module has 2 MB of L2 cache shared between the two cores. In all, Trinity, with its two modules, has 4 MB of L2 cache without any L3 cache.