News Posts matching #Foveros

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Intel Zooms in on "Lakefield" Foveros Package

The fingernail-size Intel chip with Foveros technology is a first-of-its kind. With Foveros, processors are built in a totally new way: not with the various IPs spread out flat in two dimensions, but with them stacked in three dimensions. Think of a chip designed as a layer cake (a 1-millimeter-thick layer cake) versus a chip with a more-traditional pancake-like design. Intel's Foveros advanced packaging technology allows Intel to "mix and match" technology IP blocks with various memory and I/O elements - all in a small physical package for significantly reduced board size. The first product designed this way is "Lakefield," the Intel Core processor with Intel hybrid technology.

Industry analyst firm The Linley Group recently named Intel's Foveros 3D-stacking technology as "Best Technology" in its 2019 Analysts' Choice Awards. "Our awards program not only recognizes excellence in chip design and innovation, but also acknowledges the products that our analysts believe will have an impact on future designs," said Linley Gwennap, of The Linley Group.

Intel Xe Graphics to Feature MCM-like Configurations, up to 512 EU on 500 W TDP

A reportedly leaked Intel slide via DigitalTrends has given us a load of information on Intel's upcoming take on the high performance graphics accelerators market - whether in its server or consumer iterations. Intel's Xe has already been cause for much discussion in a market that has only really seen two real competitors for ages now - the coming of a third player with muscles and brawl such as Intel against the already-established players NVIDIA and AMD would surely spark competition in the segment - and competition is the lifeblood of advancement, as we've recently seen with AMD's Ryzen CPU line.

The leaked slide reveals that Intel will be looking to employ a Multi-Chip-Module (MCM) approach to its high performance "Arctic Sound" graphics architecture. The GPUs will be available in up to 4-tile configuration (the name Intel is giving each module), which will then be joined via Foveros 3D stacking (first employed in Intel Lakefield. This leaked slide shows Intel's approach starting with a 1-tile GPU (with only 96 of its 128 total EUs active) for the entry level market (at 75 W TDP) a-la DG1 SDV (Software Development Vehicle).

Intel Core i5-L16G7 is the first "Lakefield" SKU Appearance, Possible Prelude to New Nomenclature?

Intel Core i5-L16G7 is the first commercial SKU that implements Intel's "Lakefield" heterogenous x86 processor architecture. This 5-core chip features one high-performance "Sunny Cove" CPU core, and four smaller "Tremont" low-power cores, with an intelligent scheduler balancing workloads between the two core types. This is essentially similar to ARM big.LITTLE. The idea being that the device idles most of the time, when lower-powered CPU cores can hold the fort; performance cores kick in only when really needed, until which time they remain power-gated. Thai PC enthusiast TUM_APISAK discovered the first public appearance of the i5-L16G7 in an unreleased Samsung device that has the Userbenchmark device ID string "SAMSUNG_NP_767XCL."

Clock speeds of the processor are listed as "1.40 GHz base, with 1.75 GHz turbo," but it's possible that the two core types have different clock-speed bands, just like the cores on big.LITTLE SoCs. Other key components of "Lakefield" include an iGPU based on the Gen11 graphics architecture, and an LPDDR4X memory controller. "Lakefield" implements Foveros packaging, in which high-density component dies based on newer silicon fabrication nodes are integrated with silicon interposers based on older fabrication processes, which facilitate microscopic high-density wiring between the dies. In case of "Lakefield," the Foveros package features a 10 nm "compute field" die sitting atop a 22 nm "base field" interposer.

Intel Announces New GPU Architecture and oneAPI for Unified Software Stack at SC19

At Supercomputing 2019, Intel unveiled its vision for extending its leadership in the convergence of high-performance computing (HPC) and artificial intelligence (AI) with new additions to its data-centric silicon portfolio and an ambitious new software initiative that represents a paradigm shift from today's single-architecture, single-vendor programming models.

Addressing the increasing use of heterogeneous architectures in high-performance computing, Intel expanded on its existing technology portfolio to move, store and process data more effectively by announcing a new category of discrete general-purpose GPUs optimized for AI and HPC convergence. Intel also launched the oneAPI industry initiative to deliver a unified and simplified programming model for application development across heterogenous processing architectures, including CPUs, GPUs, FPGAs and other accelerators. The launch of oneAPI represents millions of Intel engineering hours in software development and marks a game-changing evolution from today's limiting, proprietary programming approaches to an open standards-based model for cross-architecture developer engagement and innovation.

Intel Unveils New Tools in Its Advanced Chip Packaging Toolbox

What's New: This week at SEMICON West in San Francisco, Intel engineering leaders provided an update on Intel's advanced packaging capabilities and unveiled new building blocks, including innovative uses of EMIB and Foveros together and a new Omni-Directional Interconnect (ODI) technology. When combined with Intel's world-class process technologies, new packaging capabilities will unlock customer innovations and deliver the computing systems of tomorrow.

"Our vision is to develop leadership technology to connect chips and chiplets in a package to match the functionality of a monolithic system-on-chip. A heterogeneous approach gives our chip architects unprecedented flexibility to mix and match IP blocks and process technologies with various memory and I/O elements in new device form factors. Intel's vertically integrated structure provides an advantage in the era of heterogeneous integration, giving us an unmatched ability to co-optimize architecture, process and packaging to deliver leadership products." -Babak Sabi, Intel corporate vice president, Assembly and Test Technology Development.
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