This week at the Electronic Components Technology Conference (ECTC), Intel introduced EMIB-T, an important upgrade to its embedded multi-die interconnect bridge packaging. First showcased at the Intel Foundry Direct Connect 2025 event, EMIB-T incorporates through-silicon vias (TSVs) and high-power metal-insulator-metal capacitors into the existing EMIB structure. According to Dr. Rahul Manepalli, Intel Fellow and vice president of Substrate Packaging Development, these changes allow a more reliable power supply and stronger communication between separate chiplets. Conventional EMIB designs have struggled with voltage drops because of their cantilevered power delivery paths. In contrast, EMIB-T routes power directly through TSVs from the package substrate to each chiplet connection. The integrated capacitors compensate for fast voltage fluctuations and preserve signal integrity.

This improvement will be critical for next-generation memory, such as HBM4 and HBM4e, where data rates of 32 Gb/s per pin or more are expected over a UCIe interface. Intel has confirmed that the first EMIB-T packages will match the current energy efficiency of around 0.25 picojoules per bit while offering higher interconnect density. The company plans to reduce the bump pitch below today's standard of 45 micrometers. Beginning in 2026, Intel intends to produce EMIB-based packages measuring 120 by 120 millimeters, roughly eight times the size of a single reticle. These large substrates could integrate up to twelve stacks of high-bandwidth memory alongside multiple compute chiplets, all connected by more than twenty EMIB bridges. Looking further ahead, Intel expects to push package dimensions to 120 by 180 millimeters by 2028. Such designs could accommodate more than 24 memory stacks, eight compute chiplets, and 38 or more EMIB bridges. These developments closely mirror similar plans announced by TSMC for its CoWoS technology. In addition to EMIB-T, Intel also presented a redesigned heat spreader that reduces voids in the thermal interface material by approximately 25%, as well as a new thermal-compression bonding process that minimizes warping in large package substrates.

Intel says its struggling Foundry division will finally break even in 2027, just as its advanced 14A process comes online. The announcement came during the J.P. Morgan Global Technology, Media & Communications Conference, where CFO David Zinsner outlined the plan to offset years of quarterly losses. Intel has been pouring billions of dollars into new fabs and equipment as it races to keep pace with TSMC and Samsung. Its first milestone is the 18A process, whose first product, codenamed Panther Lake, will arrive in client PCs late in 2025, with volume production following in 2026. Intel also plans to use 18A for its next Xeon "Clearwater Forest" server chips and offer it to a small set of external partners to prove the technology's readiness. "We have to start by using our own chips," Zinsner explained. "Once we show that Panther Lake and Clearwater Forest perform as expected, we'll see more interest from outside customers for 18A, 18A‑P, and then 14A."

He acknowledged that initial adoption is low, but expressed confidence that proven performance will drive committed volume. A key part of the strategy is the use of High‑NA EUV lithography at 14A. Zinsner admitted this will raise equipment costs at first, but he believes the improved transistor density and power efficiency will more than make up for the investment, boosting margins and factory utilization. Intel's path to break even also incorporates revenue from mature nodes such as Intel 16/12, advanced packaging services, and collaborations with UMC and Tower. Under its "smart capital" model, the company will balance internal wafer demand with third‑party work, maintaining flexibility and cost discipline. With a relatively modest external revenue target (for a cash-bleeding foundry), low to mid single‑digit billions per year, Intel Foundry aims to reach break‑even in 2027 and move into sustained profitability soon afterward. By 2027, Intel 14A node and ehnaced the 1.8 nm-class 18A-P(T) node will also complement these break-even efforts.

According to Chosun Biz, Intel Foundry client acquisition efforts for the 18A node have shifted into high gear, with the latest reports indicating that Microsoft has inked a substantial foundry deal based on the 18A process. Talks with Google are also said to be advancing, suggesting that Intel may soon secure a second cloud giant for a customer of its 18A technology. Intel's flagship 18A node, which entered risk production earlier this year, is slated for full-scale volume manufacturing before the end of 2025. Beyond the baseline 18A offering, the company is already developing two enhanced variants: 18A-P, scheduled for rollout in 2026, and 18A-PT, targeted for 2028. Chosun Biz reports that prototype 18A-P wafers have been produced in Intel's domestic fabs, pointing out the foundry's swift pace of new node production.

Intel has even begun sharing early PDKs for its next-generation 14A node with select partners, paving the way for continued scaling beyond the 18A era. Strategically, Intel's extensive US fab footprint, which includes two under-construction fabs in Arizona (a USD 32 billion investment), expanded packaging facilities in New Mexico, a new 300 mm logic plant in Oregon, and two Ohio fabs earmarked for the early 2030s, could prove advantageous amid ongoing tariff uncertainties. Beyond North America, Intel is gearing up Fab 34 in Ireland for mass production of its Intel 4 node and inaugural 3 nm chips later this year. In Israel, Fab 38 is being outfitted for EUV-based, high-performance wafer manufacturing, while an advanced packaging site in Penang, Malaysia, supports global assembly and testing.

Siemens Digital Industries Software today announced that its continued collaboration with Intel Foundry has resulted in multiple product certifications, updated foundry reference flows, and additional technology enablement leveraging the foundry's leading-edge technologies for next-generation integrated circuits (IC) and advanced packaging. Siemens is a founding partner of the Intel Foundry Accelerator Chiplet Alliance - enabling a new and compelling solution for 3D IC and chiplet offerings to a breadth of semiconductor market verticals.

Intel 18A Certification Achievements
Siemens' industry-leading Calibre nmPlatform tool is now certified for the latest Intel 18A production Process Design Kit (PDK). Intel 18A represents a significant technological leap forward, featuring innovative RibbonFET Gate-all-around transistors and the industry's first PowerVia backside power delivery. This Calibre certification allows mutual customers to continue leveraging the Calibre nmPlatform tool as their industry-standard sign-off solution with Intel Foundry's most advanced manufacturing process, accelerating time-to-market for next-generation chip designs.

Ansys today announced thermal and multiphysics signoff tool certifications for designs manufactured with Intel 18A process technology. These certifications help ensure functionality and reliability of advanced semiconductor systems for the most demanding applications—including AI chips, graphic processing units (GPUs), and high-performance computing (HPC) products. Intel Foundry and Ansys have also enabled a comprehensive multiphysics signoff analysis flow for Intel Foundry's EMIB technology used for creating multi-die 3D integrated circuit (3D-IC) systems.

Recognized as industry-leading solutions, RedHawk-SC and Totem deliver speed, accuracy, and capacity to analyze the power integrity and reliability of Intel 18A RibbonFET Gate-all-around (GAA) transistors with PowerVia backside power delivery. For scalable electromagnetic analysis, Ansys is introducing HFSS-IC Pro, a new addition to the HFSS-IC product family. HFSS-IC Pro is certified for modeling on-chip electromagnetic integrity in radio frequency chips, Wi-Fi, 5G/6G, and other telecommunication applications made with the Intel 18A process node.

Today at Intel Foundry Direct Connect, the company will share progress on multiple generations of its core process and advanced packaging technologies. The company will also announce new ecosystem programs and partnerships, and welcome industry leaders to discuss how a systems foundry approach enables collaboration with partners and unlocks innovation for customers.

Intel CEO Lip-Bu Tan will open the event by discussing Intel Foundry's progress and priorities as the company drives the next phase of its foundry strategy. Naga Chandrasekaran, Intel Foundry chief technology and operations officer, and Kevin O'Buckley, general manager of Foundry Services, will also deliver keynotes during the morning session, sharing process and advanced packaging news while highlighting Intel Foundry's globally diverse manufacturing and supply chain.

At today's Intel Foundry Direct Connect 2025 event, Synopsys, Inc. announced broad EDA and IP collaborations with Intel Foundry, including availability of its certified AI-driven digital and analog design flows for the Intel 18A process node and production-ready EDA flows for the Intel 18A-P process node with RibbonFET Gate-all-around transistor architecture and the industry's first commercial foundry implementation of PowerVia backside power delivery. To drive multi-die design innovation forward, Synopsys and Intel Foundry are collaborating to enable Intel's new Embedded Multi-die Interconnect Bridge-T (EMIB-T) advanced packaging technology with an EDA reference flow powered by Synopsys 3DIC Compiler. With its EDA flows, multi-die solution, and broad portfolio of Synopsys' foundation and interface IP on Intel 18A and Intel 18A-P, Synopsys is helping designers accelerate the development of highly optimized AI and HPC chip designs from silicon to systems.

In a keynote presentation at today's event, John Koeter, Senior Vice President, for the Synopsys IP Group, emphasized: "The successful collaboration between Synopsys and Intel Foundry is advancing the semiconductor industry with silicon to system design solutions to meet the evolving needs for AI and high-performance computing applications. Our production-ready EDA flows, IP, and multi-die solution, provides our mutual customers with comprehensive technologies to accelerate the development of chip designs that meet or exceed their requirements."

Cadence today announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification of Cadence digital and analog/custom design solutions for the latest Intel 18A process design kit (PDK). These advancements are being showcased today at Intel Foundry Direct Connect, underscoring Cadence's continued leadership in driving industry innovation for artificial intelligence and machine learning (AI/ML), high-performance computing (HPC) and advanced mobility applications through its strategic partnership with Intel Foundry.

Cadence has collaborated closely with Intel Foundry to design and optimize a comprehensive range of solutions that fully leverage the innovative features of the Intel 18A/18A-P nodes, including RibbonFET Gate-all-around transistors and PowerVia backside power delivery network. With this collaboration, joint customers can achieve exceptional power, performance and area (PPA) efficiencies, accelerating time to market for cutting-edge system-on-chip (SoC) designs.

As revealed during a recent Q1 earnings call, Intel leadership mentioned that "external clients are getting their ASICs designs tested." The company's foundry business is working towards the finalization of its much discussed 18A node process, with alleged trial samples receiving an "impressive performance rating." According to Ctee Taiwan, Team Blue's foundry service has submitted test subjects to the likes of NVIDIA, Broadcom and Faraday Technology. The latter organization has (reportedly) disclosed that the 18A platform tape-out was completed last October—since then, received samples have been "successfully connected." Industry moles believe that NVIDIA and Broadcom are in the middle of conducting manufacturing tests. Additional whispers suggest the delivery of 18A prototypes chez IBM and several other unnamed partner companies. Insiders have indicated impressive/good "verification results." Contrary to reports from other sources, Ctee has picked up on insider chatter about Intel's next-gen Nova Lake compute tile design being "not entirely outsourced." Further conjecture points to Team Blue becoming increasingly confident in its own manufacturing techniques.

Intel just reported its Q1 revenue results, and there are several interesting highlights from the earnings call. Intel Foundry, long touted for a comeback, is generating most of its revenue from a single customer, and it isn't the latest node. Intel's biggest customer is actually itself, predominantly using the "Intel 7" node (Intel's name for its 10 nm SuperFin process), which underpins the Alder Lake and Raptor Lake consumer CPU generations as well as the Sapphire Rapids Xeon server generation. As Intel ramps up 18A-node production and external clients begin testing their ASIC designs, 18A still isn't the Foundry division's primary revenue driver. Instead, demand for Intel 7 wafers is being fueled by massive orders for Intel's 13th- and 14th-generation Raptor Lake processors.

During the Q1 earnings call, Intel CFO Dave Zinsner noted, "Intel Foundry delivered revenue of $4.7 billion, up 8% sequentially on pull-ins of Intel 7 wafers and increased advanced packaging services." He also commented on the Q1 Foundry operating loss of $2.3 billion, attributing it to "startup costs associated with the ramp of products on Intel 18A." While the 18A node is gradually scaling to volume production for upcoming internal and external products, older nodes continue to fuel the revenue stream. Zinsner further confirmed that "we have a lot of important building blocks in place, including the ramp of Intel 18A in the second half of 2025 to support the launch of our first Panther Lake SKU by year-end, with additional SKUs coming in the first half of 2026."

Intel's freshly concluded Vision 2025 "Products Update and GTM" showcase included a segment dedicated to forthcoming Core Ultra 300 "Panther Lake" client processors. Industry watchdogs have grabbed a select few screenshots from Team Blue's broadcast from Las Vegas, Nevada—one backdropped slide confirms that Intel's next-generation mobile CPU series will launch in 2026. This information mirrors the company's Chinese office presenting of an AI PC roadmap—coverage of last month's event highlighted a scheduled first quarter 2026 "volume" arrival of "Core Ultra Next-gen Panther Lake (18A)."

Going back to early March, Intel leadership refuted online rumors of "Panther Lake" mobile CPUs being delayed into 2026, due to alleged problems encountered during the development of the Foundry service's 18A process node. An interviewed executive repeatedly insisted that his firm's brand-new series was on track for release within the second half of 2025. Fast-forward to the end of last week; Lip-Bu Tan expressed a similar outlook in a letter addressed to investors. The newly-established boss stated: "we will further enhance our (leadership) position in the second half of this year with the launch of Panther Lake, our lead product on Intel 18A, followed by Nova Lake in 2026." Industry insiders propose that the Core Ultra 300 series will become available in a very limited capacity come October, via an Early Enablement Program (EEP). Returning to this week—Jim Johnson, senior vice president of the firm's Client Computing Group, informed a watchful audience about the merits of his group's design: "I'm personally excited about Panther Lake because it combines the power efficiency of Lunar Lake, the performance of Arrow Lake, and is built to scale 18A and is on track for production later this year...Our client roadmap is the most innovative we've ever had, and we are far from done."

Intel and SK Hynix have finalized an $8.85 billion transaction involving Intel's NAND flash memory operations, marking the conclusion of a two-phase deal initiated in 2020. In the first phase of the transaction, SK Hynix acquired Intel's SSD division along with a NAND production facility in Dalian, China, for $6.61 billion. The Dalian facility was later rebranded as Solidigm. Notably, this phase transferred only the physical assets and operational facilities, leaving behind critical intellectual property, research and development infrastructure, and specialized technical staff. The second phase, finalized with a payment of $1.9 billion this Tuesday, addressed these remaining components. With this payment, SK Hynix secured full rights to Intel's proprietary NAND technology, R&D resources, and the technical workforce dedicated to NAND operations.

During the transition period, Intel maintained control over these elements, which limited integration between Solidigm and Intel's NAND teams. This separation was designed to manage operational risks and gradually transfer capabilities. Completing this deal helps with a strategic restructuring of Intel's portfolio as it shifts focus toward high-growth areas such as AI chip development, foundry services, and next-generation semiconductor manufacturing. A $1.9 billion financial injection is perfect in time for Intel Foundry business, burning billions per year, to offset some of the losses. For SK Hynix, consolidating the complete range of Intel's NAND operations enhances its competitive position in the global NAND market, providing access to established technologies and key industry expertise. This finalization is part of a broader trend where companies divest from commoditized memory products to concentrate on more advanced semiconductor solutions like AI chips and other accelerators, which are enjoying higher margins and a better business outlook.

Intel just started a succession of its Foundry division management. According to an Intel spokesperson for Tom's Hardware, Dr. Ann Kelleher is heading for retirement after spending 30 years at Intel. Dr. Kelleher is the executive vice president of Intel Foundry and has been the head of foundry technology development since 2020. For the past 30 years, Dr. Kelleher has been there for Intel's ups and downs, overcoming many challenges for the company. This year, Dr. Kelleher's impressive 30-year run at Intel is coming to an end as she heads to a well-deserved retirement. While not being active, her immense knowledge and education are still valuable, and she will remain a board advisor.

Succeeding her at the head of the Foundry front-end division will be Naga Chandrasekaran, who brings over three decades of semiconductor experience, 20 of which have been spent at Micron. Assisting Naga Chandrasekaran with back-end foundry operations like packaging will be Navid Shahriari, who spent over 35 years at Intel and is currently a senior vice president. In a statement for Tom's Hardware, Intel noted: "As previously announced, Dr. Ann Kelleher plans to retire later this year following a distinguished career spanning over 30 years with Intel. With a strong foundry leadership team in place and Intel 18A progressing well ahead of our first product launch and external customer tape-outs, this is a well-planned transition as we continue to advance our Foundry priorities in service to customers."

At the time of crisis for Intel and uncertainty with foundry goals, Intel has appointed a semiconductor veteran as its new Chief Executive Officer (CEO)—Lip-Bu Tan. In a letter to Intel employees, Lip-Bu Tan has quietly addressed Intel Foundry spinoff rumors, saying that his commitment as a CEO is to "restore Intel's position as a world-class products company, establish ourselves as a world-class foundry and delight our customers like never before." Hence, the foundry spinoff rumors are now not so certain. Previous industry rumors suggested that Intel may very well spin off its fabs entirely or get it in a joint venture that would see TSMC and US companies like AMD, Broadcom, and NVIDIA get a part of the say. That is still a possibility. However, Intel's new CEO understands the strategic importance of Intel's fabs, just like the previous CEO, Pat Gelsinger.

Intel moves a lot of volume with its products, most of that thanks to its internal manufacturing capacity. Without it, Intel would be forced to go to external fabs like Samsung and TSMC and deal with additional complexity, lead times, etc. With the 18A node, Intel plans to use it for its products and offer it to external customers. Some features like backside power delivery using PowerVia and RibbonFET are standout aspects that make its 18A node PDK much more attractive on paper than solutions from TSMC and Samsung. Keeping that technology and manufacturing ability inside Intel is strategically vital for both Intel and US-based advanced silicon manufacturing. The foundry has been burning a lot of cash, 13.4 billion in 2024 alone, but Intel expects it to be net positive by the end of 2027. After that, Intel's products and external customers should be keeping Intel's fab busy with enough revenue to offset losses in the coming years.