News Posts matching "Interconnect"

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Latest Intel Roadmap Slide Leaked, Next Core X is "Cascade Lake-X"

The latest version of Intel's desktop client-platform roadmap has been leaked to the web, which reveals timelines and names of the company's upcoming product lines. To begin with, it states that Intel will upgrade its Core X high-end desktop (HEDT) product line only in Q4-2018. The new Core X HEDT processors will be based on the "Cascade Lake-X" silicon. This is the first appearance of the "Cascade Lake" micro-architecture. Intel is probably looking to differentiate its Ringbus-based multi-core processors (eg: "Coffee Lake," "Kaby Lake") from ones that use Mesh Interconnect (eg: "Skylake-X"), so people don't compare the single-threaded / less-parallized application performance between the two blindly.

Next up, Intel is poised to launch its second wave of 6-core, 4-core, and 2-core "Coffee Lake" processors in Q1-2018, with no mentions of an 8-core mainstream-desktop processor joining the lineup any time in 2018. These processors will be accompanied by more 300-series chipsets, namely the H370 Express, B360 Express, and H310 Express. Q1-2018 also sees Intel update its low-power processor lineup, with the introduction of the new "Gemini Lake" silicon, with 4-core and 2-core SoCs under the Pentium Silver and Celeron brands.

Source: MyDrivers

PCI SIG Releases PCI-Express Gen 4.0 Specifications

The Peripheral Component Interconnect (PCI) special interest group (SIG) published the first official specification (version 1.0) of PCI-Express gen 4.0 bus. The specification's previous draft 0.9 was under technical review by members of the SIG. The new generation PCIe comes with double the bandwidth of PCI-Express gen 3.0, reduced latency, lane margining, and I/O virtualization capabilities. With the specification published, one can expect end-user products implementing it. PCI SIG has now turned its attention to the even newer PCI-Express gen 5.0 specification, which will be close to ready by mid-2019.

PCI-Express gen 4.0 comes with 16 GT/s bandwidth per-lane, per-direction, which is double that of gen 3.0. An M.2 NVMe drive implementing it, for example, will have 64 Gbps of interface bandwidth at its disposal. The SIG has also been steered toward lowering the latencies of the interconnect as HPC hardware designers are turning toward alternatives such as NVLink and InfinityFabric, not primarily for the bandwidth, but the lower latency. Lane margining is a new feature that allows hardware to maintain a uniform physical layer signal clarity across multiple PCIe devices connected to a common root complex. This is particularly important when you have multiple pieces of mission-critical hardware (such as RAID HBAs or HPC accelerators), and require uniform performance across them. The new specification also adds new I/O virtualization features that should prove useful in HPC and cloud computing.

Intel Announces New Mesh Interconnect For Xeon Scalable, Skylake-X Processors

Intel's "Xeon Scalable" lineup is designed to compete directly with AMD's Naples platform. Naples, a core-laden, high performance server platform that relies deeply on linking multiple core complexes together via AMD's own HyperTransport derived Infinity Fabric Interconnect has given intel some challenges in terms of how to structure its own high-core count family of devices. This has led to a new mesh-based interconnect technology from Intel.

Tech Industry Leaders Unite, Unveil New High-Perf Server Interconnect Technology

On the heels of the recent Gen-Z interconnect announcement, an aggregate of some of the most recognizable names in the tech industry have once again banded together. This time, it's an effort towards the implementation of a fast, coherent and widely compatible interconnect technology that will pave the way towards tighter integration of ever-more heterogeneous systems.

Technology leaders AMD, Dell EMC, Google, Hewlett Packard Enterprise, IBM, Mellanox Technologies, Micron, NVIDIA and Xilinx announced the new open standard to appropriate fanfare, considering the promises of an up-to 10x performance uplift in datacenter server environments, thus accelerating big-data, machine learning, analytics, and other emerging workloads. The interconnect promises to provide a high-speed pathway towards tighter integration between different types of technology currently making up the heterogeneous server computing's needs, ranging through fixed-purpose accelerators, current and future system memory subsistems, and coherent storage and network controllers.
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