AMD is already looking ahead to its Zen 7 generation and is planning the final details for its next generation of Zen IP. The first hints come from YouTuber "Moore's Law Is Dead," which points to a few interesting decisions. AMD plans to extend its multi‑class core strategy that began with Zen 4c and continued into Zen 5. Zen 7 will reportedly include three types of cores: the familiar performance cores, dense cores built for maximum throughput, and a new low‑power variant aimed at energy‑efficient tasks, just like Intel and its LP/E-Cores. There is even an unspecified "PT" and "3D" core. By swapping out pipeline modules and tweaking their internal libraries, AMD can fine‑tune each core so it performs best in its intended role, from running virtual machines in the cloud to handling AI workloads at the network edge.

On the manufacturing front, Zen 7 compute chiplets (CCDs) are expected to be made on TSMC's A14 process, which will now include a backside power delivery network. This was initially slated for the N2 node but got shifted to the A16/A14 line. The 3D V‑Cache SRAM chiplets underneath the CCDs will remain on TSMC's N4 node. It is a conservative choice, since TSMC has talked up using N2‑based chiplets for stacked memory in advanced packaging, but AMD appears to be playing it safe. Cache sizes should grow, too. Each core will get 2 MB of L2 cache instead of the current 1 MB, and L3 cache per core could expand to 7 MB through stacked V‑Cache slices. Standard CCDs without V‑Cache will still have around 32 MB of shared L3. A bold rumor suggests an EPYC model could feature 33 cores per CCD, totaling 264 cores across eight CCDs. Zen 7 tape‑out is planned for late 2026 or early 2027, and we probably won't see products on shelves until 2028 or later. As always with early-stage plans, take these details with a healthy dose of skepticism. The final Zen 7 lineup could look quite different once AMD locks down its roadmap.

Late last month, data miners unearthed a wide variety of unannounced AMD Ryzen processor IPs. A "Sound Wave" product category received less attention, but Team Red's curious codename has reemerged in the middle of May. Thanks to fresh Kepler L2 theorizations, this mysterious mobile APU family has a potential end destination. Leaks from 2024 suggested that company engineers were working on an unusual Arm-based processor branch. AMD is cozily well-versed in all things x86, but an alleged present day diversification—into Arm (x64) territories—has confounded a fair few industry watchdogs.

In a tangential conversation—forking off from speculative "Zen 6" and PlayStation 6 APU chatter—Kepler L2 reckons that Team Red "Sound Wave" chips will be deployed in 2026, possibly within a refreshed Microsoft Surface lineup. Current-gen Arm-based offerings—leveraging Qualcomm Snapdragon X processors—have generated mixed user impressions (press and public alike). Microsoft and Qualcomm's "Windows on Arm" (WoA) platform partnership was elevated earlier on in May (with cheaper options), but troublesome hardware-to-software compatibility issues have reportedly caused some rifts in this relationship. As of last week, evaluators seemed to be poking around with NVIDIA's rumored Arm-based "N1" chip series on Windows. In theory, AMD's futuristic "Sound Wave" designs could do battle with (claimed) Team Green and MediaTek collaborative efforts.

Closer to the start of 2025, Kepler L2 shared "PlayStation 6" inside track info. The venerable leaker—of mostly AMD behind-the-scenes details—theorized that Sony's sixth-gen home console was based around an early fork that branched off from a mysterious "GFX13" GPU architecture. Earlier today, this target identifier has appeared again. Kepler L2's latest investigations have pulled the "GFX13+" target from kernel-level codebase updates. Data miners have often pulled compelling pre-release tidbits from official repositories; AMD's software engineering team open-source developments are quite visible. Over a year ago, similar detective work connected the "GFX12" IP to RDNA 4—nowadays, better known as the Radeon RX 9000 graphics card family. Despite Team Red's official insistence that RDNA 4 was a priority on desktop platforms, supposed discrete mobile variants were leaked last month. In addition, RDNA 3.5 seems to be a mainstay for at least another generation of integrated graphics solutions.

Looking beyond these current-gen graphics architectures, AMD leadership has already previewed a "unified" path forward. Last September's announcement revealed the convergence of RDNA (gaming) and CDNA (enterprise) GPU technologies: dubbed "UDNA." Present day leaks do mention a far out "RDNA 5" line (also "Navi 5x"), but in the same sentence as "UDNA." Kepler L2 commented on the (screen captured) presence of "ENABLE_WAVEFRONT" and "ENABLE_WAVEGROUP" kernel code properties: "I think it's related to SWC (Streaming Wave Coalescer/pseudo out-of-order execution). Each SIMD takes multiple wave32/wave64 (a wavegroup) as inputs and reorders the work items of each wave to reduce execution divergence." Fresh rumors suggest the distant RDNA 5/UDNA avenue being good enough to expand into higher-end gaming card territories. So far, RDNA 4 has hit a ceiling with Navi 48 GPU-powered Radeon 9070 XT offerings.

Die shots of Intel's "Arrow Lake" desktop processors have appeared online, confirming the chiplet design we have known about since the launch. The images annotated by the YouTube channel HighYield show a four‑tile arrangement mounted on a base die made with Intel's 22 nm FinFET process. The compute tile sits at the top left, built on TSMC's N3B node and covering 117.24 mm². To its right are the SoC tile on TSMC's N6 node measuring 86.65 mm², and the GPU tile, which houses four Xe cores alongside an Arc Alchemist render slice. The I/O tile, at 24.48 mm² on the same N6 node, completes the group at the bottom left. Intel has redesigned its hybrid core layout for Arrow Lake, moving away from separate P‑core and E‑core clusters. Four of the eight high‑performance P‑cores line the die's outer edges, with the remaining four in the center. In between these lie the four efficiency E‑core clusters, each sharing 3 MB of L2 cache. A unified 36 MB L3 cache ring bus connects to every core, allowing E‑cores to tap into that larger cache pool for the first time. Intel aims to spread heat more evenly and boost background task performance.

The I/O tile integrates Thunderbolt 4 controllers, PCIe buffers and PHYs. The SoC tile carries display engines, media accelerators and DDR5 memory controllers. All tiles are bonded to the base die via Intel's Foveros Omni stacking technology. Arrow Lake also reflects a shift in Intel's manufacturing strategy. Plans to use Intel's 20A node were dropped in favor of TSMC processes, making this the first desktop CPU from Intel that relies almost entirely on external foundries. On the software side, Intel has begun offering its IPO profiles in select prebuilt systems. These presets optimize CPU and memory settings for a hassle‑free performance boost that remains within warranty limits. Meanwhile, the native 200S Boost overclocking option is rolling out via BIOS updates. Early tests suggest that 200S Boost alone yields modest gains unless paired with very high-speed DDR5 modules, while IPO profiles deliver more consistent improvements with mainstream memory configurations.

AMD has confirmed pricing and launch for its newest Ryzen 9000X3D series processors, with the flagship 9950X3D priced at approximately 5599 RMB and the 9900X3D at 4599 RMB, according to preliminary Chinese store JD listings. Both processors will hit retail channels on March 12, with review embargoes reportedly lifting one day prior, as noted by VideoCardz. The Ryzen 9 9950X3D delivers 16 Zen 5 cores with boost frequencies reaching 5.7 GHz and operates within a 170 W TDP envelope. Its unique feature is 144 MB of combined cache memory (L2, L3, and stacked 3D V-Cache).

The 9900X3D scales back to 12 cores with 5.5 GHz peak frequencies and 140 MB total cache while reducing power consumption to 120 W TDP. These processors represent AMD's implementation of vertical cache stacking technology on its 12+ core Zen 5 setup, completing its Q1 2025 desktop portfolio expansion following earlier standard Ryzen 9000 series launches and the eight-core Ryzen 7 9800X3D. The 3D V-Cache technology could help with many workloads, with gaming performance expected to show the most significant gains and productivity expected to follow. We have to wait for official reviews to bring further conclusions, but we hope to hear official confirmation on availability soon.

NVIDIA's upcoming RTX 5090 and 5080 graphics cards are maintaining similar L1 cache architectures as their predecessors while introducing marginal improvements to L2 cache capacity, according to recent specifications reported by HardwareLuxx. The flagship RTX 5090 maintains the same 128 KB L1 cache per SM as the RTX 4090 but achieves a higher total L1 cache of 21.7 MB thanks to its increased SM count of 170. This represents a notable improvement over the RTX 4090's 16.3 MB total L1 cache, which features 128 SMs. In terms of L2 cache, the RTX 5090 sees a 33.3% increase over its predecessor, boasting 96 MB compared to the RTX 4090's 72 MB, with SM count going up by 32.8%, so there is a slight difference.

However, this improvement is relatively modest compared to the previous generation's leap, where the RTX 4090 featured twelve times more L2 cache than the RTX 3090. The RTX 5080 shows more conservative improvements, with its L1 cache capacity only marginally exceeding its predecessor by 1 MB (10.7 MB vs 9.7 MB). Its L2 cache maintains parity at 64 MB, matching the RTX 4080 and 4080 Super. To compensate for these incremental cache improvements, NVIDIA is implementing faster GDDR7 memory across the RTX 50 series. Most models will feature 28 Gbps modules, with the RTX 5080 receiving special treatment with 30 Gbps memory. Additionally, some models are getting wider memory buses, with the RTX 5090 featuring a 512-bit bus and the RTX 5070 Ti upgrading to a 256-bit interface.

AMD is preparing to release its next generation of high-performance CPUs, the Ryzen 9000X3D series, and rumors are circulating about potential increases in stacked L3 cache. However, a recent report from Wccftech suggests that the upcoming models will maintain the same 64 MB of additional 3D V-cache as their predecessors. The X3D moniker represents AMD's 3D V-Cache technology, which vertically stacks an extra L3 cache on top of one CPU chiplet. This design has proven particularly effective in enhancing gaming performance, leading AMD to market these processors as the "ultimate gaming" solutions. According to the latest information, the potential Ryzen 9 9950X3D would feature 16 Zen 5 cores with a total of 128 (64+64) MB L3 cache, while a Ryzen 9 9900X3D would offer 12 cores with the same cache capacity. The Ryzen 7 9800X3D is expected to provide 96 (32+64) MB of total L3 cache.

Regarding L2, the CPUs feature one MB of L2 cache per core. Perhaps the most exciting development for overclockers is the reported inclusion of full overclocking support in the new X3D series. This marks a significant evolution from the limited options available in previous generations, potentially allowing enthusiasts to push these gaming-focused chips to new heights of performance. While the release date for the Ryzen 9000X3D series remains unconfirmed, industry speculation suggests a launch window as early as September or October. This timing would coincide with the release of new X870 (E) chipset motherboards. PC enthusiasts would potentially wait to match the next-gen CPU and motherboards, so this should be a significant upgrade cycle for many.

NVIDIA's H800 AI GPU was rolled out last year to appease the Sanction Gods—but later on, the US Government deemed the cutdown "Hopper" part to be far too potent for Team Green's Chinese enterprise customers. Last October, newly amended export conditions banned sales of the H800, as well as the slightly older (plus similarly gimped) A800 "Ampere" GPU in the region. NVIDIA's engineering team returned to the drawing board, and developed a new range of compliantly weakened products. An exclusive Reuters report suggests that Team Green is taking pre-orders for a refreshed "Hopper" GPU—the latest China-specific flagship is called "HGX H20." NVIDIA web presences have not been updated with this new model, as well as Ada Lovelace-based L20 PCIe and L2 PCIe GPUs. Huawei's competing Ascend 910B is said to be slightly more performant in "some areas"—when compared to the H20—according to insiders within the distribution network.

The leakers reckon that NVIDIA's mainland distributors will be selling H20 models within a price range of $12,000 - $15,000—Huawei's locally developed Ascend 910B is priced at 120,000 RMB (~$16,900). One Reuters source stated that: "some distributors have started advertising the (NVIDIA H20) chips with a significant markup to the lower end of that range at about 110,000 yuan ($15,320). The report suggests that NVIDIA refused to comment on this situation. Another insider claimed that: "distributors are offering H20 servers, which are pre-configured with eight of the AI chips, for 1.4 million yuan. By comparison, servers that used eight of the H800 chips were sold at around 2 million yuan when they were launched a year ago." Small batches of H20 products are expected to reach important clients within the first quarter of 2024, followed by a wider release in Q2. It is believed that mass production will begin around Spring time.