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Intel Launches 12th Gen Core "Alder Lake" HX Processors (8P+8E cores on Mobile)

Intel today debuted the 12th Gen Core HX "Alder Lake" processors for high-end gaming notebooks and mobile workstations. These processors are designed to bring desktop-class performance to the mobile segment, and debut the "Alder Lake" C0 silicon in a mobile package. Until now, the fastest Core "Alder Lake" mobile processor was based on a silicon that physically had 6 performance cores (P-cores), and 8 efficiency cores (E-cores). The HX-series sees the desktop C0 silicon, with its 8 P-cores and 8 E-cores, and 30 MB of L3 cache, in the mobile form factor.

This also brings PCI-Express 5.0 x16 PEG connectivity for discrete graphics cards, 8-lane DMI 4.0 chipset bus, and a mobile variant of the Z690 chipset, which can put out two M.2 NVMe Gen 4 slots in addition to the one from the processor die. The additional PCIe budget should allow up to two discrete Thunderbolt 4 controllers. Memory support includes dual-channel (4 sub-channel) DDR5-4800, dual-channel DDR4-3200, and LPDDR4-4267. Certain models even have ECC memory support, targeted at mobile workstations. Intel is using the highest bins of the C0 die, coupled with some aggressive power-management, to achieve processor base power (PBP) of 55 W (10 W lower than the 65 W PBP of the desktop Core i9-12900). The maximum turbo power value for all SKUs is set at 154 W. All processor models in the Core HX series will come with memory overclocking support, some even with CPU overclocking support.

NVIDIA Hopper Whitepaper Reveals Key Specs of Monstrous Compute Processor

The NVIDIA GH100 silicon powering the next-generation NVIDIA H100 compute processor is a monstrosity on paper, with an NVIDIA whitepaper published over the weekend revealing its key specifications. NVIDIA is tapping into the most advanced silicon fabrication node currently available from TSMC to build the compute die, which is TSMC N4 (4 nm-class EUV). The H100 features a monolithic silicon surrounded by up to six on-package HBM3 stacks.

The GH100 compute die is built on the 4 nm EUV process, and has a monstrous transistor-count of 80 billion, a nearly 50% increase over the GA100. Interestingly though, at 814 mm², the die-area of the GH100 is less than that of the GA100, with its 826 mm² die built on the 7 nm DUV (TSMC N7) node, all thanks to the transistor-density gains of the 4 nm node over the 7 nm one.

NVIDIA RTX 40-series "Ada" GPUs to Stick to PCI-Express Gen 4

NVIDIA's next-generation GeForce "Ada" graphics architecture may stick to PCI-Express 4.0 as its system bus interface, according to kopite7kimi, a reliable source with NVIDIA leaks. This is unlike Ada's sister-architecture for compute, "Hopper," which leverages PCI-Express 5.0 in its AIC form-factor cards, for its shared memory pools and other resource-sharing features similar to CXL. This would make Ada the second graphics architecture from NVIDIA to use PCIe Gen 4, after the current-gen "Ampere." The previous-gen "Turing" used PCIe Gen 3. PCI-Express 4.0 x16 offers 32 GB/s per-direction bandwidth, and NVIDIA has implemented the Resizable-BAR feature with "Ampere," which lets the system see the entire dedicated video memory as one addressable block, rather than through tiny 256 MB apertures.

Despite using PCI-Express 4.0 for its host interface, GeForce "Ada" graphics cards are expected to extensively use the ATX 3.0 spec 16-pin power connector that the company debuted with the RTX 3090 Ti, particularly with higher-end GPUs that have typical board power above 225 W. The 16-pin connector is being marketed as a "PCIe Gen 5" generation standard, particularly by PSU manufacturers cashing in on early-adopter demand. All eyes are now on AMD's RDNA3 graphics architecture, on whether it's first to market with PCI-Express Gen 5, the way RDNA (RX 5000 series) was with PCIe Gen 4. The decision to stick with PCIe Gen 4 is particularly interesting given that Microsoft DirectStorage may gain use in the coming years, something that is expected to strain the system bus for the GPU, as SSD I/O transfer-rates increase with M.2 PCIe Gen 5 SSDs.

AMD EPYC "Genoa" Zen 4 Processor Multi-Chip Module Pictured

Here is the first picture of a next-generation AMD EPYC "Genoa" processor with its integrated heatspreader (IHS) removed. This is also possibly the first picture of a "Zen 4" CPU Complex Die (CCD). The picture reveals as many as twelve CCDs, and a large sIOD silicon. The "Zen 4" CCDs, built on the TSMC N5 (5 nm EUV) process, look visibly similar in size to the "Zen 3" CCDs built on the N7 (7 nm) process, which means the CCD's transistor count could be significantly higher, given the transistor-density gained from the 5 nm node. Besides more number-crunching machinery on the CPU core, we're hearing that AMD will increase cache sizes, particularly the dedicated L2 cache size, which is expected to be 1 MB per core, doubling from the previous generations of the "Zen" microarchitecture.

Each "Zen 4" CCD is reported to be about 8 mm² smaller in die-area than the "Zen 3" CCD, or about 10% smaller. What's interesting, though, is that the sIOD (server I/O die) is smaller in size, too, estimated to measure 397 mm², compared to the 416 mm² of the "Rome" and "Milan" sIOD. This is good reason to believe that AMD has switched over to a newer foundry process, such as the TSMC N7 (7 nm), to build the sIOD. The current-gen sIOD is built on Global Foundries 12LPP (12 nm). Supporting this theory is the fact that the "Genoa" sIOD has a 50% wider memory I/O (12-channel DDR5), 50% more IFOP ports (Infinity Fabric over package) to interconnect with the CCDs, and the mere fact that PCI-Express 5.0 and DDR5 switching fabric and SerDes (serializer/deserializers), may have higher TDP; which together compel AMD to use a smaller node such as 7 nm, for the sIOD. AMD is expected to debut the EPYC "Genoa" enterprise processors in the second half of 2022.

AMD SP5 EPYC "Genoa" Zen4 Processor Socket Pictured in the Flesh

Here's the first picture of AMD Socket SP5, the huge new CPU socket the company is building its next-generation EPYC "Genoa" enterprise processors around. "Genoa" will be AMD's first server products to implement the new "Zen 4" CPU cores, and next-gen I/O, including DDR5 memory and PCI-Express Gen 5. SP5, much like its predecessor SP3, is a land-grid array (LGA) socket, and has 6,096 pins.

The vast pin-count enables power to support CPU core-counts of up to 96 on the EPYC "Genoa," and up to 128 on the EPYC "Bergamo" cloud processor; a 12-channel DDR5 memory interface (24 sub-channels); and up to 128 PCI-Express 5.0 lanes. The socket's retention mechanism and processor installation procedure appears similar to that of the SP3, although the thermal requirements of SP5 will be entirely new, with processors expected to ship with TDP as high as 400 W, compared to 280 W on the current-generation EPYC "Milan." AMD is expected to debut EPYC "Genoa" in the second half of 2022.

Intel "Sapphire Rapids" Xeon 4-tile MCM Annotated

Intel Xeon Scalable "Sapphire Rapids" is an upcoming enterprise processor with a CPU core count of up to 60. This core-count is achieved using four dies inter-connected using EMIB. Locuza, who leads social media with logic die annotation, posted one for "Sapphire Rapids," based on a high-resolution die-shot revealed by Intel in its ISSCC 2022 presentation.

Each of the four dies in "Sapphire Rapids" is a fully-fledged multi-core processor in its own right, complete with CPU cores, integrated northbridge, memory and PCIe interfaces, and other platform I/O. What brings four of these together is the use of five EMIB bridges per die. This allows CPU cores of a die to transparantly access the I/O and memory controlled any of the other dies transparently. Logically, "Sapphire Rapids" isn't unlike AMD "Naples," which uses IFOP (Infinity Fabric over package) to inter-connect four 8-core "Zeppelin" dies, but the effort here appears to be to minimize the latency arising from an on-package interconnect, toward a high-bandwidth, low-latency one that uses silicon bridges with high-density microscopic wiring between them (akin to an interposer).

EVGA Announces the Z690 DARK KINGPIN Motherboard

Introducing the EVGA Z690 DARK K|NGP|N - The Motherboard Designed by and Used by Professional Overclockers. EVGA DARK motherboards blaze the trail for other boards to follow, and the Z690 DARK K|NGP|N is no exception. The ability to destroy world records is insignificant next to the power of a 21-phase VRM and a 10-layer PCB - capable of driving the most powerful 12th Gen Intel Core processors. With support for 64 GB of DDR5 memory at up to 6600 MHz+(OC), PCIe Gen5, and PCIe Gen4 M.2 NVMe SSDs, a new DARK age of overclocking will rise as quickly as new hardware becomes available. The Z690 DARK K|NGP|N is today's choice for the future of overclocking and gaming.

MSI and Phison Partner to Launch Spatium E26 PCIe Gen5 AIC SSD

Phison is on a mission to be the first to market with PCIe Gen 5 SSD controllers, having announced the E26-series controllers this CES. The company is ready with a branded drive under the MSI Spatium brand, the MSI Spatium E26. Built in the PCIe add-in-card (AIC) form-factor, the drive features a PCI-Express 5.0 x4 interface (128 Gbps per direction), and very likely sticks to the reference design that Phison demoed in its own booth.

This PCB is used in its client configuration, with just the controller, DRAM, and NAND flash chips; while the PCB allows an enterprise configuration with banks of capacitors offering explicit power-loss protection (the NAND flash chips offer implicit PLP). A simple copper-film heatspreader is used. Neither MSI nor Phison put out actual performance numbers, but mentioned sequential reads being "10 GB/s or beyond" (the interface is physically capable of 16 GB/s).

Update Jan 17th: MSI clarified that this is not yet a shipping product, but a representation of what such a device could be. Thus, this should be considered a concept or at best proof of concept. Both MSI and Phison are actively working together on exploring what such a retail product could be.

ASRock Launches H670, B660 and H610 Motherboards

ASRock, is proud to announce its latest H670, B660 and H610 motherboards. This comprehensive range of feature-filled motherboards is designed to bring great performance and practicality - including up to PCI-Express 5.0 - to PC builders, gamers and office users looking to partner with either just launched Intel 12th Generation Core 'non-K series' processors, or existing K-series processors (LGA1700).

ASRock offers SFF builders a full range of Mini-ITX motherboards featuring H670, B660, H610 chipsets. The fully-featured ASRock H670M-ITX/ax includes support for future PCI-Express 5.0 16x graphics cards, plus space for two PCI-Express Gen-4 M.2 NVMe SSDs. A powerful 8-phase Dr.MOS VRM design and up to DDR4 5000 MHz OC means ensures small form factor builds still offer maximum performance. Three types of connectivity include extreme performance Wi-Fi 6E (2x2), Dragon 2.5G LAN and Intel Gigabit Ethernet.

Phison Unveils E26, the Company's First PCIe Gen5 Controller for High-end Desktop Gaming

Phison Electronics Corp., a global leader in NAND flash controller integrated circuits and storage solutions, will showcase its lineup of next-generation gaming solutions for customers, partners, media and other interested parties during CES 2022, January 5-8 exclusively by private virtual demos. The new-class of solutions include the company's first PCIe Gen5 controller for high-end desktop gaming, a future high-performance Gen4 solution, and demonstration of the next-generation game workload coming soon to PCs.

Phison, the leader in gaming-optimized SSDs pushes the boundaries of performance. The company's solutions power seamless experiences for modern console, desktop/notebook and mobile gaming, which are delivered to consumers through an extensive and diverse group of partners.
Update Jan 4th: Added presentation slides, product images and closeups of the PCB designs.

Intel H670, B660, and H610 Chipset Features Leaked

Intel is preparing to significantly expand its 12th Gen Core "Alder Lake" desktop processor series next January, alongside more motherboard chipset choices for the client-desktop segment. These include the H670, the B660, and the H610. The H670 offers most of the I/O features of the top Z690 chipset, but you lose out on CPU overclocking. The B660 is the mid-tier option, and while you still get a formidable I/O feature-set, the chipset bus is narrower. The H610 is the entry-level chipset with very basic I/O, and no CPU-attached NVMe slots. The interesting thing is that all these chipsets support PCI-Express 5.0 x16 (PEG) from the CPU, but leave it to the motherboard vendors whether they want to implement it. There do exist Z690 motherboard that lack Gen 5 PEG (and only feature Gen 4).

The chipset-attached downstream PCIe also varies greatly across the lineup. The top Z690 part puts out 12 Gen 4 lanes besides 16 Gen 3 lanes; while the H670 puts out 12 each of Gen 4 and Gen 3. The B660 puts out 6 Gen 4 lanes and 8 Gen 3 lanes. The H610 completely lacks downstream Gen 4, and only puts out 8 Gen 3 lanes. The H670 and B660 put out up to two 20 Gbps USB 3.2 Gen 2x2 ports; while the H610 lacks 20 Gbps ports. All chipset models put out at least two 10 Gbps Gen 2x1 ports; and at least four 5 Gbps Gen 1x1 ports. An interesting aspect of the lineup is that Intel is allowing memory overclocking across H670 and B660 chipsets, provided the CPU supports it.

Intel "Meteor Lake" Chips Already Being Built at the Arizona Fab

With its 12th Gen Core "Alder Lake-P" mobile processors still on the horizon, Intel is already building test batches of the 14th Gen "Meteor Lake" mobile processors, at its Fab 42 facility in Chandler, Arizona. "Meteor Lake" is a multi-chip module that leverages Intel's Foveros packaging technology to combine "tiles" (purpose built dies) based on different silicon fabrication processes depending on their function and transistor-density/power requirements. It combines four distinct tiles across a single package—the compute tile, with the CPU cores; the graphics tile with the iGPU: the SoC I/O tile, which handles the processor's platform I/O; and a fourth tile, which is currently unknown. This could be a memory stack with similar functions as the HBM stacks on "Sapphire Rapids," or something entirely different.

The compute tile contains the processor's various CPU core types. The P cores are "Redwood Cove," which are two generations ahead of the current "Golden Cove." If Intel's 12-20% generational IPC uplift cadence holds, we're looking at cores with up to 30% higher IPC than "Golden Cove" (50-60% higher than "Skylake."). "Meteor Lake" also debuts Intel's next-generation E-core, codenamed "Crestmont." The compute tile is rumored to be fabricated on the Intel 4 node (optically a 7 nm-class node, but with characteristics similar to TSMC N5).

GIGABYTE Z690 AERO D Combines Function with Absolute Form

GIGABYTE's AERO line of motherboards and notebooks target creators who like to game. The company is ready with a premium motherboard based on the Intel Z690 chipset, the Z690 AERO D. This has to be the prettiest looking motherboard we've come across in a long time, and it appears to have the chops to match this beauty. The Socket LGA1700 motherboard uses large ridged-aluminium heatsinks over the chipset, M.2 NVMe slots, and a portion of the rear I/O shroud. Aluminium fin-stack heatsinks fed by heat-pipes, cool the CPU VRM. You get two PCI-Express 5.0 x16 slots (x8/x8 with both populated). As an AERO series product, the board is expected to be loaded with connectivity relevant to content creators, although the box is missing a Thunderbolt logo. We expect at least 20 Gbps USB 3.2x2 ports, and 10 GbE networking, Wi-Fi 6E.

KIOXIA CD7 Series PCIe 5.0 SSDs Belt Out 14 GBps Sequential Transfers

Presenting at the China Flash-Market Summit, KIOXIA unveiled its plans to leverage PCI-Express 5.0 to double SSD performance over the current generation. In typical 4-lane U.2 and M.2 connections, PCI-Express Gen 5 enables an interface bandwidth of 16 GB/s per direction (comparable to PCI-Express 3.0 x16). This means that accounting for interface overheads, typical PCIe Gen 5 SSDs will dance around the 11-15 GB/s (sequential) range. KIOXIA unveiled the CD7, a prototype enterprise SSD in the 2.5-inch EDSFF E3S form-factor with U.2 PCI-Express 5.0 x4 interface. This drive, the company claims, offers up to 14 GB/s sequential transfers, more than double the performance of the current CM6 series drives that leverage PCI-Express Gen 4.

KIOXIA said that its first PCI-Express Gen 5 SSDs will begin shipping in Q4-2021, although it didn't mention if this was mass-market, or to select customers. The first enterprise platforms to leverage Gen 5 won't arrive before mid-2022, with Intel's Xeon "Sapphire Rapids" processors that feature PCI-Express Gen 5 support. KIOXIA sounded optimistic about the future growth in performance of SSDs. "Today, Moore's Law is technically dead in both the CPU and DRAM, but it still works at the PCIe clock rate," the company said, adding ""2015 [was] be the third generation of PCIe, 2019 is the fourth generation, and 2022 will be the fifth generation. Even if people spend a lot of money, they can't double CPU nodes to improve system performance, but buying Gen 5 SSD instead of Gen 4 SSD can greatly improve system performance."

Xilinx Versal HBM Series with Integrated High Bandwidth Memory Tackles Big Data Compute Challenges in the Network and Cloud

Xilinx, Inc., the leader in adaptive computing, today introduced the Versal HBM adaptive compute acceleration platform (ACAP), the newest series in the Versal portfolio. The Versal HBM series enables the convergence of fast memory, secure connectivity, and adaptable compute in a single platform. Versal HBM ACAPs integrate the most advanced HBM2E DRAM, providing 820 GB/s of throughput and 32 GB of capacity for 8X more memory bandwidth and 63% lower power than DDR5 implementations. The Versal HBM series is architected to keep up with the higher memory needs of the most compute intensive, memory bound applications for data center, wired networking, test and measurement, and aerospace and defense.

"Many real-time, high-performance applications are critically bottlenecked by memory bandwidth and operate at the edge of their power and thermal limits," said Sumit Shah, senior director, Product Management and Marketing at Xilinx. "The Versal HBM series eliminates those bottlenecks to provide our customers with a solution that delivers significantly higher performance and reduced system power, latency, form factor, and total cost of ownership for data center and network operators."

Intel "Alder Lake" CPU Core Segmentation Sketched

Intel's 12th Gen Core "Alder Lake-S" desktop processors in the LGA1700 package could see the desktop debut of Intel's Hybrid Technology that it introduced with the mobile segment "Lakefield" processor. Analogous to Arm big.LITTLE, Intel Hybrid Technology is a multi-core processor topology that sees the combination of high-performance CPU cores with smaller high-efficiency cores that keep the PC ticking through the vast majority of the time/tasks when the high-performance cores aren't needed and hence power-gated. The high-performance cores are woken up only as needed. "Lakefield" combines one "Sunny Cove" high-performance core with four "Tremont" low-power cores. "Alder Lake-S" will take this concept further.

According to Intel slides leaked to the web by HXL (aka @9550pro), the 10 nm-class "Alder Lake-S" silicon will physically feature 8 "Golden Cove" high-performance cores, and 8 "Gracemont" low-power cores, along with a Gen12 iGPU that comes in three tiers - GT0 (iGPU disabled), GT1 (some execution units disabled), and GT2 (all execution units enabled). In its top trim with 125 W TDP, "Alder Lake-S" will be a "16-core" processor with 8 each of "Golden Cove" and "Gracemont" cores enabled. There will be 80 W TDP models with the same 8+8 core configuration, which are probably "locked" parts. Lastly, there the lower wrungs of the product stack will completely lack "small" cores, and be 6+0, with only high-performance cores. A recurring theme with all parts is the GT1 trim of the Gen12 iGPU.

Intel's Gargantuan Next-gen Enterprise CPU Socket is LGA4677

Intel has finalized design of its next-generation Xeon Scalable enterprise CPU socket for its "Sapphire Rapids" processors. Called LGA4677, the socket succeeds LGA3647, and is bound for a 2021 market release. Intel will have transitioned to its advanced 7 nm EUV silicon fabrication node on the CPU front, and has adopted an "enterprise-first" strategy for the node. LGA4677 will be designed to handle the extremely high bandwidth of PCI-Express Gen 5, which doubles bandwidth over PCIe gen 4.0, and adds several enterprise-specific features Intel is rolling out in advance as part of its CXL interconnect. These details, along with a prototype LGA4189 socket, was revealed at an exhibit by TE Connectivity, a company that manufactures the socket. The additional pin-count could enable Intel to not just deploy PCI-Express Gen 5, but also expand I/O in other directions, such as more memory channels, dedicated Persistent Memory I/O, etc.

PCI-SIG Achieves 32 GT/s with New PCI-Express 5.0 Specification

PCI-SIG today announced the release of PCI Express (PCIe ) 5.0 specification, reaching 32 GT/s transfer rates, while maintaining low power and backwards compatibility with previous technology generations. "New data-intensive applications are driving demand for unprecedented levels of performance," said Al Yanes, PCI-SIG Chairman and President. "Completing the PCIe 5.0 specification in 18 months is a major achievement, and it is due to the commitment of our members who worked diligently to evolve PCIe technology to meet the performance needs of the industry. The PCIe architecture will continue to stand as the de facto standard for high performance I/O for the foreseeable future."

"For 27 years, the PCI-SIG has continually delivered new versions of I/O standards that enable designers to accommodate the never-ending increases in bandwidth required for next generation systems, while preserving investments in prior generation interfaces and software," noted Nathan Brookwood, research fellow at Insight 64. "Over that period, peak bandwidth has increased from 133 MB/second (for the first 32-bit parallel version) to 32 GB/second (for the V4.0 by16 serial version), a 240X improvement. Wow! The new PCIe 5.0 standard doubles that again to 64 GB/second. Wow2. We have come to take this increased performance for granted, but in reality, it takes a coordinated effort across many members of the PCI-SIG to execute these transitions so seamlessly."

Intel Releases Compute Express Link (CXL) 1.0, New Interconnect Protocol that Enables PCIe gen 5.0

Intel has been working on CXL, short for Compute Express Link gen 1, for over four years new. This new interconnect protocol was donated to a new consortium of tech companies for release as a the CXL 1.0 standard. Its protocol layer will pave the way for PCI-Express gen 5.0 to sustain its bandwidth growth target of being twice as fast as PCIe gen 4.0. CXL 1.0 is out to compete with other established PCIe-alternative slot standards such as NVLink from NVIDIA, and InfinityFabric from AMD. It has one killer advantage, though: the CXL 1.0 is pin-compatible and backwards-compatible with PCI-Express, and uses PCIe physical-layer and electrical interface.

This reduces hardware upgrade costs for data-centers. CXL maintains memory coherency between the CPU's memory-space and memory on installed devices. The CXL Consortium, or SIG, includes data-center and cloud-computing giants, including Alibaba, Cisco, DellEMC, Facebook, Google, HPE, Huawei, Microsoft, and of course Intel. CXL will be used bot as a socketed/slotted interface for add-on cards and GPU boards, and as an embedded interface. We estimate bandwidth of CXL to be 32 Gbps per lane, or four times that of PCIe gen 3.0, keeping in line with PCIe gen 5.0 bandwidth growth estimates.

PCI-SIG Fast Tracks Evolution to 32 GT/s with PCI Express 5.0 Architecture

PCI-SIG Developers Conference 2017 - PCI-SIG, the organization responsible for the widely adopted PCI Express (PCIe) industry-standard input/output (I/O) technology, today announced 32GT/s as the next progression in speed for the PCIe 5.0 architecture, targeting high-performance applications such as artificial intelligence, machine learning, gaming, visual computing, storage and networking. Slated for completion in 2019, the specification development is well underway with Revision 0.3 already available to PCI-SIG member companies.

"In our 25-year history, PCI-SIG has maintained its commitment to our rigorous specification development process, while delivering specifications that are in lock-step with industry requirements for high-performance I/O," said Al Yanes, PCI-SIG Chairman and President. "PCIe 5.0 technology is the next evolution that will set the standard for speed, and we are confident that its 32GT/s bandwidth will surpass industry needs."

The preceding PCIe 4.0 specification is designed with key functional enhancements that future-proof the PCIe architecture design, thereby accelerating future specification development. This undertaking, along with improved silicon design processes, serves as the foundation for the PCIe 5.0 specification.
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