News Posts matching #PCIe 5.0

Return to Keyword Browsing

Europe Readies its First Prototype of Custom HPC Processor

European Processor Initiative (EPI) is a Europe's project to kickstart a homegrown development of custom processors tailored towards different usage models that the European Union might need. The first task of EPI is to create a custom processor for high-performance computing applications like machine learning, and the chip prototypes are already on their way. The EPI chairman of the board Jean-Marc Denis recently spoke to the Next Platform and confirmed some information regarding the processor design goals and the timeframe of launch.

Supposed to be manufactured on TSMC's 6 nm EUV (TSMC N6 EUV) technology, the EPI processor will tape-out at the end of 2020 or the beginning of 2021, and it is going to be heterogeneous. That means that on its 2.5D die, many different IPs will be present. The processor will use a custom ARM CPU, based on a "Zeus" iteration of Neoverese server core, meant for general-purpose computation tasks like running the OS. When it comes to the special-purpose chips, EPI will incorporate a chip named Titan - a RISC-V based processor that uses vector and tensor processing units to compute AI tasks. The Titan will use every new standard for AI processing, including FP32, FP64, INT8, and bfloat16. The system will use HBM memory allocated to the Titan processor, have DDR5 links for the CPU, and feature PCIe 5.0 for the inner connection.

PCI-SIG Achieves 32 GT/s with New PCI-Express 5.0 Specification

PCI-SIG today announced the release of PCI Express (PCIe ) 5.0 specification, reaching 32 GT/s transfer rates, while maintaining low power and backwards compatibility with previous technology generations. "New data-intensive applications are driving demand for unprecedented levels of performance," said Al Yanes, PCI-SIG Chairman and President. "Completing the PCIe 5.0 specification in 18 months is a major achievement, and it is due to the commitment of our members who worked diligently to evolve PCIe technology to meet the performance needs of the industry. The PCIe architecture will continue to stand as the de facto standard for high performance I/O for the foreseeable future."

"For 27 years, the PCI-SIG has continually delivered new versions of I/O standards that enable designers to accommodate the never-ending increases in bandwidth required for next generation systems, while preserving investments in prior generation interfaces and software," noted Nathan Brookwood, research fellow at Insight 64. "Over that period, peak bandwidth has increased from 133 MB/second (for the first 32-bit parallel version) to 32 GB/second (for the V4.0 by16 serial version), a 240X improvement. Wow! The new PCIe 5.0 standard doubles that again to 64 GB/second. Wow2. We have come to take this increased performance for granted, but in reality, it takes a coordinated effort across many members of the PCI-SIG to execute these transitions so seamlessly."

PCI-SIG: PCIe 4.0 in 2017, PCIe 5.0 in 2019

After years of continued innovation in PCIe's bandwidth, we've hit somewhat of a snag in recent times; after all, the PCIe 3.0 specification has been doing the rounds on our motherboards ever since 2010. PCI-SIG, the 750-member strong organization that's in charge of designing the specifications for the PCIe bus, attribute part of this delay to industry stagnation: PCIe 3.0 has simply been more than enough, bandwidth-wise, for many generations of hardware now. Only recently, with innovations in storage mediums and innovative memory solutions, such as NVMe SSDs and Intel's Optane, are we starting to hit the ceiling on what PCIe 3.0 offers. Add to that the increased workload and bandwidth requirements of the AI field, and the industry now seems to be eager for an upgrade, with some IP vendors even having put out PCIe 4.0-supporting controllers and PHYs into their next-generation products already - although at the incomplete 0.9 revision.
Return to Keyword Browsing