ScaleFlux, a leader in deploying computational storage at scale, today announced its commitment to integrating the Arm Cortex -R82 processor in its forthcoming line of enterprise Solid State Drive (SSD) controllers. The Cortex-R82, is the highest performance real-time processor from Arm and the first to implement the 64-bit Armv8-R AArch64 architecture, representing a significant advancement in processing power and efficiency for enterprise storage solutions.

ScaleFlux's adoption of the Cortex-R82 is a strategic move to leverage the processor's high performance and energy efficiency. This collaboration underscores ScaleFlux's dedication to delivering cutting-edge technology in its SSD controllers, enhancing data processing capabilities and efficiency for data center and AI infrastructure worldwide.

Nubis Communications, Inc., provider of low-latency high-density optical inter-connect (HDI/O), and Alphawave Semi (LN: AWE), a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, today announced their upcoming demonstration of PCI Express 6.0 technology driving over an optical link at 64GT/s per lane. Data Center providers are exploring the use of PCIe over Optics to greatly expand the reach and flexibility of the interconnect for memory, CPUs, GPUs, and custom silicon accelerators to enable more scalable and energy-efficient clusters for Artificial Intelligence and Machine Learning (ML/AI) architectures.

Nubis Communications and Alphawave Semi will be showing a live demonstration in the Tektronix booth at DesignCon, the leading conference for advanced chip, board, and system design technologies. An Alphawave Semi PCIe Subsystem with PiCORE Controller IP and PipeCORE PHY will directly drive and receive PCIe 6.0 traffic through a Nubis XT1600 linear optical engine to demonstrate a PCIe 6.0 optical link at 64GT/s per fiber, with optical output waveform measured on a Tektronix sampling scope with a high-speed optical probe.

Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity for the world's technology infrastructure, today announced successful collaboration with Keysight Technologies, a market-leading design, emulation, and test solutions provider, demonstrating interoperability between Alphawave Semi's PCIe 6.0 64 GT/s Subsystem (PHY and Controller) Device and Keysight PCIe 6.0 64 GT/s Protocol Exerciser, negotiating a link to the maximum PCIe 6.0 data rate. Alphawave Semi, already on the PCI-SIG 5.0 Integrators list, is accelerating next-generation PCIe 6.0 Compliance Testing through this collaboration.

Alphawave Semi's leading-edge silicon implementation of the new PCIe 6.0 64 GT/s Flow Control Unit (FLIT)-based protocol enables higher data rates for hyperscale and data infrastructure applications. Keysight and Alphawave Semi achieved another milestone by successfully establishing a CXL 2.0 link setting the stage for future cache coherency in the datacenter.

Phison Electronics, a global leader in NAND controllers and storage solutions, announced today that the company has expanded its portfolio of PCIe 5.0 high-speed transmission solutions with PCIe 5.0, CXL 2.0 compatible redriver and retimer data signal conditioning IC products. Leveraging the company's deep expertise in PCIe engineering, Phison is the only signal conditioners provider that offers the widest portfolio of multi-channel PCIe 5.0 redriver and retimer solutions and PCIe 5.0 storage solutions designed specifically to meet the data infrastructure demands of artificial intelligence and machine learning (AI+ML), edge computing, high-performance computing, and other data-intensive, next-gen applications. At the 2023 Open Compute Project Global Summit, the Phison team is showcasing its expansive PCIe 5.0 portfolio, demonstrating the redriver and retimer technologies alongside other enterprise NAND flash, illustrating a holistic vision for a PCIe 5.0 data ecosystem to address the most demanding applications of the AI-everywhere era.

"Phison has focused industry-leading R&D efforts on developing in-house, chip-to-chip communication technologies since the introduction of the PCIe 3.0 protocol, with PCIe 4.0 and PCIe 5.0 solutions now in mass production, and PCIe 6.0 solutions now in the design phase," said Michael Wu, President & General Manager, Phison US. "Phison's accumulated experience in high-speed signaling enables our team to deliver retimer and redriver design solutions that are optimized for top signal integration, low power usage, and high temperature endurance, to deliver interface speeds for the most challenging compute environments."

Ever since the creation of A64FX for the Fugaku supercomputer, Fujitsu has been plotting the development of next-generation CPU design for accelerating AI and general-purpose HPC workloads in the data center. Codenamed Monaka, the CPU is the latest creation for TSMC's 2 nm semiconductor manufacturing node. Based on Armv9-A ISA, the CPU will feature up to 150 cores with Scalable Vector Extensions 2 (SVE2), so it can process a wide variety of vector data sets in parallel. Using a 3D chiplet design, the 150 cores will be split into different dies and placed alongside SRAM and I/O controller. The current width of the SVE2 implementation is unknown.

The CPU is designed to support DDR5 memory and PCIe 6.0 connection for attaching storage and other accelerators. To bring cache coherency among application-specific accelerators, CXL 3.0 is present as well. Interestingly, Monaka is planned to arrive in FY2027, which starts in 2026 on January 1st. The CPU will supposedly use air cooling, meaning the design aims for power efficiency. Additionally, it is essential to note that Monaka is not a processor that will power the post-Fugaku supercomputer. The post-Fugaku supercomputer will use post-Monaka design, likely iterating on the design principles that Monaka uses and refining them for the launch of the post-Fugaku supercomputer scheduled for 2030. Below are the slides from Fujitsu's presentation, in Japenese, which highlight the design goals of the CPU.

Join us for the PCI-SIG Developers Conference in Santa Clara, CA and see demos of the latest Rambus PCI Express (PCIe ) 6.0 IP solutions, including 64 Gigatransfers per second (GT/s) PCIe 6.0 PHY and Controller IP. With leading PPA, these 64 GT/s products achieve high performance, low power and area-efficient footprint for compute-intensive workloads including data center, AI/ML and HPC applications.

The Rambus PCIe 6.0 Interface Subsystem comprising PHY and Controller has been fully optimized to meet the needs of advanced heterogenous computing architectures. The PCIe Controller features an Integrity and Data Encryption (IDE) engine dedicated to protecting the PCIe links and the valuable data transferred over them. The PCIe 6.0 PHY features state-of-the-art SI/PI performance to provide best-in-class design margin for first-time-right implementations.

Analyst firm Yole Group has predicted that SSD sales revenues will grow to $67 billion in the year 2028, generated by 472 million unit sales - indicating a very healthy outlook in the long term. However, their predictions for market performance in 2023 appear to be less cheerful for manufacturers of NAND flash memory. The SSD market dynamic was positive in 2021 and the starting months of 2022, but demand has dropped sharply since then due to a number of factors including global inflation, geopolitical tensions, and inventory digestion at electronics manufacturers. Sales revenues in 2022 totaled $29 billion (352 million units), down from $34 billion (400 million units) in 2021 - demonstrating a 14% year-to-year decline.

The continued weakening of global demand in 2023 will have an effect on SSD sales revenues, and the Yole Group has foreseen troublesome outcomes for manufacturers. The average selling price of NAND memory and solid-state drive units has been on the decline in the recent quarters, caused by sluggish demand and a surplus of stock. Despite the grim outlook in the short term, the research body is predicting a compounded annual growth rate (CAGR) of about 15% between 2022 and 2028 for the overall size of the SSD market.

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced the availability of its PCI Express (PCIe) 6.0 Interface Subsystem comprised of PHY and controller IP. The Rambus PCIe Express 6.0 PHY also supports the latest version of the Compute Express Link (CXL) specification, version 3.0. "The rapid advancement of AI/ML and data-intensive workloads is driving the continued evolution of data center architectures requiring ever higher levels of performance," said Scott Houghton, general manager of Interface IP at Rambus. "The Rambus PCIe 6.0 Interface Subsystem supports the performance requirements of next-generation data centers with premier latency, power, area and security."

The Rambus PCIe 6.0 Interface Subsystem delivers data rates of up to 64 Gigatransfers per second (GT/s) and has been fully optimized to meet the needs of advanced heterogenous computing architectures. Within the subsystem, the PCIe controller features an Integrity and Data Encryption (IDE) engine dedicated to protecting the PCIe links and the valuable data transferred over them. On the PHY side, full support for CXL 3.0 is available to enable chip-level solutions for cache-coherent memory sharing, expansion and pooling.

Tektronix, Inc., introduces the industry's first PCI Express 6.0 compatible Base transmitter test solution just weeks after the PCI-SIG working group released PCI Express (PCIe) 6.0 Base specifications and validation requirements. PCIe 6.0 is an important and scalable standard for data-intensive markets such as data center, artificial intelligence/machine learning (AI/ML), and high-performance computing. To meet ever growing performance demands, PCIe 6.0 standard transitions to PAM4 signaling and new innovative error correcting techniques. The Tektronix test solution includes PCIe 6.0 measurement-specific software, enhanced PAM4 DSP capabilities and noise compensation on the oscilloscope for increased accuracy of results. The Tektronix test solution for PCIe 6.0 standard is further enhanced by the industry-leading analysis tools for SNDR and uncorrelated jitter measurements which are both mandated requirements for the PCIe 6.0 standard.

The industry's first PCIe 6.0 standard transmitter validation solution is focused on serving high-performance and data-intensive markets and is available worldwide for use with DPO70000SX ATI Performance Oscilloscopes. "Tektronix' PCIe 6.0 standard test solution came to market quickly because of the company's deep involvement in the PCI-SIG working group, where it helped define the standard's measurement methodologies," said David Bouse, PCI Express Principal Technology Lead at Tektronix and PCI-SIG working group participant.

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced the availability of its PCI Express (PCIe ) 6.0 Controller. The PCIe specification is the interconnect of choice across a broad landscape of data-intensive markets including data center, AI/ML, HPC, automotive, IoT, defense and aerospace. Optimized for power, area and latency, the Rambus PCIe 6.0 controller delivers data rates up to 64 Gigatransfers per second (GT/s) for high-performance applications. In addition, the controller provides state-of-the-art security with an Integrity and Data Encryption (IDE) engine that monitors and protects PCIe links against physical attacks.

"The rapid advancement of AI/ML and data-intensive workloads requires that we continue to provide higher data rate solutions with best-in-class latency, power and area," said Sean Fan, chief operating officer at Rambus. "As the latest addition to our portfolio of industry-leading interface IP, our PCIe 6.0 Controller offers customers an easy to integrate solution that delivers both performance and security for advanced SoCs and FPGAs."

PCI-SIG, the organization responsible for the widely adopted PCI Express (PCIe ) standard, today announced the official release of the PCIe 6.0 specification, reaching 64 GT/s. PCI Express technology has served as the de facto interconnect of choice for nearly two decades. The PCIe 6.0 specification doubles the bandwidth and power efficiency of the PCIe 5.0 specification (32 GT/s), while providing low latency and reduced bandwidth overhead.

"PCI-SIG is pleased to announce the release of the PCIe 6.0 specification less than three years after the PCIe 5.0 specification," said Al Yanes, PCI-SIG Chairperson and President. "PCIe 6.0 technology is the cost-effective and scalable interconnect solution that will continue to impact data-intensive markets like data center, artificial intelligence/machine learning, HPC, automotive, IoT, and military/aerospace, while also protecting industry investments by maintaining backwards compatibility with all previous generations of PCIe technology."

Back in June of 2019, the PCI-SIG announced that work had started on PCIe 6.0 and some two years and four months later, PCIe 6.0 has reached version 0.9, which equals draft spec. What this means is that companies can now start to implement PCIe 6.0 into their products, to make sure they're compliant with the draft spec, since no additional functional changes will be made, unless something major is discovered.

PCIe 6.0 will be the first PCIe standard to use PAM-4 encoding, something it shares with GDDR6 memory among other standards. What this means is that twice the data can be sent per clock cycle for 64GT/s, or twice that of PCIe 5.0. Another key feature is FEC or low-latency forward error correction, as this was implemented to maintain data integrity. PCIe 6.0 is expected to be backwards compatible with all previous versions of PCIe. The final PCIe 6.0 spec isn't likely to be finalised until early next year, based on previous standards, although the original plan was to finish ratifying the spec this year.

Synopsys, Inc. today announced the industry's first complete IP solution for the PCI Express (PCIe ) 6.0 technology that includes controller, PHY and verification IP, enabling early development of PCIe 6.0 system-on-chip (SoC) designs. Built on Synopsys' widely deployed and silicon-proven DesignWare IP for PCIe 5.0, the new DesignWare IP for PCIe 6.0 supports the latest features in the standard specification including, 64 GT/s PAM-4 signaling, FLIT mode and L0p power state. Synopsys' complete IP solution addresses evolving latency, bandwidth and power-efficiency requirements of high-performance computing, AI and storage SoCs.

To achieve the lowest latency with maximum throughput for all transfer sizes, the DesignWare Controller for PCI Express 6.0 utilizes a MultiStream architecture, delivering up to 2X the performance of a single-stream design. The Controller, with available 1024-bit architecture, allows designers to achieve 64 GT/s x16 bandwidth while closing timing at 1 GHz. In addition, the controller provides optimal flow with multiple data sources and in multi-virtual channel implementations. To facilitate accelerated testbench development with built-in verification plan, sequences and functional coverage, the VC Verification IP for PCIe uses native SystemVerilog/UVM architecture that can be integrated, configured and customized with minimal effort.

PCI-SIG has recently confirmed that version 0.7 of the PCIe 6.0 Specification has been officially released to its members. The PCI-SIG organization has already ratified the PCIe 5.0 standard and plans to release the full PCIe 6.0 specification in 2021. PCIe 6.0 will bring the same doubling in data rates seen with previous generations of the standard including a 2x improvement over PCIe 5.0, 4x boost over PCIe 4.0, and an 8x increase in speeds over the common PCIe 3.0 standard.

The organization has been speeding up its timeline for new versions of the PCIe specification with PCIe 3.0 being released in 2010 followed by PCIe 4.0 in 2017, PCIe 5.0 in 2019, and with PCIe 6.0 expected in 2021. The PCIe 6.0 standard is designed to fulfill the needs of future devices in the PC and enterprise markets such as 800 Gb/s Ethernet cards. The earliest we can expect to see PCIe 6.0 devices in the PC market would be 2023 or 2024 depending on requirements.