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MIT, Stanford Partner Towards Making CPU-Memory BUSes Obsolete

Graphene has been hailed for some time now as the next natural successor to silicon, today's most used medium for semiconductor technology. However, even before such more exotic solutions to current semiconductor technology are employed (and we are still way off that future, at least when it comes to mass production), engineers and researchers seem to be increasing their focus in one specific part of computing: internal communication between components.

Typically, communication between a computer's Central Processing Unit (CPU) and a system's memory (usually DRAM) have occurred through a bus, which is essentially a communication highway between data stored in the DRAM, and the data that the CPU needs to process/has just finished processing. The fastest CPU and RAM is still only as fast as the bus, and recent workloads have been increasing the amount of data to be processed (and thus transferred) by orders of magnitude. As such, engineers have been trying to figure out ways of increasing communication speed between the CPU and the memory subsystem, as it is looking increasingly likely that the next bottlenecks in HPC will come not through lack of CPU speed or memory throughput, but from a bottleneck in communication between those two.

Crossbar Unveils Resistive RAM Non-Volatile Memory Technology

Emerging from stealth-mode today, Crossbar, Inc., a start-up company pioneering a new category of very high capacity and high-performance non-volatile memory, unveiled its Crossbar Resistive RAM (RRAM) technology. This new generation of non-volatile memory will be capable of storing up to one terabyte (TB) of data on a single 200mm2 chip, enabling massive amounts of information, such as 250 hours of HD movies, to be stored and played back from an IC smaller than a postage stamp. Crossbar today also announced it has developed a working Crossbar memory array at a commercial fab, a major milestone in the development of new memory technology, signaling its readiness to begin the first phase of productization.

Due to its simple three-layer structure, Crossbar technology can be stacked in 3D, delivering multiple terabytes of storage on a single chip. Its simplicity, stackability and CMOS compatibility enable logic and memory to be easily integrated onto a single chip at the latest technology node, a capability not possible with other traditional or alternative non-volatile memory technologies.
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