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TSMC Expands Advanced Technology Leadership with N4P Process

TSMC today introduced its N4P process, a performance-focused enhancement of the 5-nanometer technology platform. N4P joins the industry's most advanced and extensive portfolio of leading-edge technology processes. With N5, N4, N3 and the latest addition of N4P, TSMC customers will have multiple and compelling choices for power, performance, area, and cost for its products.

As the third major enhancement of TSMC's 5 nm family, N4P will deliver an 11% performance boost over the original N5 technology and a 6% boost over N4. Compared to N5, N4P will also deliver a 22% improvement in power efficiency as well as a 6% improvement in transistor density. In addition, N4P lowers process complexity and improves wafer cycle time by reducing the number of masks. N4P demonstrates TSMC's pursuit and investment in continuous improvement of our process technologies.

Alibaba Goes Anti-x86: Open-Source RISC-V and 128-Core Arm Server Processors on the Horizon

With the x86 architecture, large hyperscale cloud providers have been experiencing all sorts of troubles, from high power consumption to the high pricing structure of these processors. Companies like Amazon Web Services (AWS) build their processors based on 3rd party instruction set architecture designs. Today, Alibaba, the Chinese giant, has announced the launch of two processors made in-house to serve everything from edge to central server processing. First in line is the RISC-V-based Xuantie series of processors, which can run anything from AliOS, FreeRTOS, RT-Thread, Linux, Android, etc., to other operating systems as well. These processors are open-source, capable of modest processing capabilities, and designed as IPs that anyone can use. You can check them out on T-Head GitHub repositories here.

The other thing that Alibaba announced is the development of a 128-core custom processor based on the Arm architecture. Called Yitian 710 server SoC, TSMC manufactures it on the company on 5 nm semiconductor node. So far, Alibaba didn't reveal any details about the SoC and what Arm cores are used. However, this signifies that the company seeks technology independence from outside sources and wants to take it all in-house. With custom RISC-V processors for lower-power tasks and custom Arm server CPUs, the whole infrastructure is covered. It is just a matter of time before Alibaba starts to replace x86 makers in full. However, given the significant number of chips that the company needs, it may not happen at any sooner date.

TSMC Confirmed to Build New Fab in Japan Together with Sony

Remember that rumour from last week about TSMC potentially building a fab in Japan and partnering up with Sony? Well, the deal is on and the fab is set to start construction in 2022, with production expected to start sometime in 2024. However, as mentioned, the fab isn't going to be using any cutting edge technology when it comes to the process node, since it's intended for imaging sensors and EV components.

The new fab is said to focus on 28 and 22 nm nodes, according to Tim Culpan, who writes for Bloomberg and who has been reporting on TSMC for at least the last decade. This is backed up by the Nikkei that reports that the US$7 billion fab will make chips in the 20-nm range, without going into further details beyond mentioning these nodes are over a decade old. That said, there are still plenty of products made on older nodes than that, as not everything has to be built on a cutting edge node and many components wouldn't benefit from a smaller node. Regardless, this fab won't help with the current shortage of components, but will hopefully lead to better availability of certain components in the future.

Sony and TSMC Said to be Planning US$7 Billion Chip Fab in Japan

There doesn't seem to be a single month where rumours about new TSMC plants around the world are popping up and this time around it looks like there might be a joint venture with Sony in Japan. According to the Nikkei, the Japanese government is likely to be involved and might foot as much as half of the US$7 billion bill.

Another much more unknown player, Japanese auto parts maker Denso is also said to be a potential participant in the new fab. Denso is said to supply Toyota among others and with a shift towards more EVs, this might not be such a strange move. The new fab is expected to be located in Kumamoto Prefecture on land owned by Sony. It should be noted that Sony already manufactures image sensors here and the factory was hit badly by a large earthquake back in 2016, which led to a global shortage of certain image sensors.

Intel CEO Cites Brexit as Reason for Chip Fab Plans in UK Not an Option

In an interview with the BBC, Intel CEO Pat Gelsinger said that the company is no longer considering the UK as a site for a chip fab, due to Brexit, something the company had apparently done prior to Brexit. Now the company is looking for a location in another EU country for a US$95 billion investment for a new semiconductor plant, as well as upgrades to its current plants in Ireland.

Although Intel had not made any firm decisions on a site location prior to Brexit, Gelsinger is quoted as saying "I have no idea whether we would have had a superior site from the UK, but we now have about 70 proposals for sites across Europe from maybe 10 different countries." He continues "We're hopeful that we'll get to agreement on a site, as well as support from the EU... before the end of this year."

TSMC Claims Some Companies are Sitting on Chip Inventories

It appears that some of the current chip shortages might be artificially induced by one or multiple companies in the chip supply chain, according to an article by TIME Magazine. The article is taking a look at the role TSMC is playing in the global chip production industry and TIME has interviewed TSMC chairman Mark Liu among others in the industry.

Mark Liu is quoted as saying "But I told them, "You are my customer's customer's customer. How could I [prioritize others] and not give you chips?"" when asked about the complaints by car makers, since they were among the first to suggest TSMC was one of the issues. Due to the various allegations against TSMC, Liu had a team collect data points to try and figure out what was going on and to see which customers were truly running low on stock and which customers that might be stockpiling for a rainy day.

Fabricating the Fabs: ASML Vision Document Predicts 300 Billion-Transistor Logic by 2030

"Moore's Law is alive and well," says ASML, in its vision document addressing investors. The company manufactures the machines that perform the actual task of silicon lithography—turning silicon discs into wafers of logic or storage chips. It highlighted the various technologies making progress, which will help its semiconductor-fabrication customers, such as TSMC and their hundreds of clients, sustain Moore's Law all the way through this decade. The company predicts SoCs with as many as 300 billion transistors by 2030. To achieve this, the company is innovating in two distinct directions—at the chip-level, to increase transistor density per chip to over 50 billion transistors; and at the system level, through packaging technology innovations, to reach that ultimate transistor count.

According to ASML's roadmap, at the turn of the decade, its technology enables 5 nm-class in production, and is at the cusp of a major breakthrough, nanosheet-FETs. which pave the way for 3 nm and 2 nm nodes, backed by EUV lithography. The journey from 2 nm to 1.5 nm will require another breakthrough, forked-nanosheets, and from 1.5 nm to 1 nm yet another breakthrough, CFET. Sub-1 nm fabrication will be possible toward the turn of this decade, thanks to 2D atomic channel technology, which is how chip-designers will be able to cram over 50 billion transistors per chip, and build MCM systems with over 300 billion transistors. The presentation predicts that besides 3D packaging, stacked silicon will also play a role, with multiple stacked logic layers, heterogenous chips with logic, storage, and I/O layers, stacked DRAM (up from single-digit layers to double-digits; and for NAND flash to grow from the current 176-layer, to nearly 500-layer by 2030.

India and Taiwan Working Towards $7.5 billion Chip Plant Deal

There's no secret that Taiwan has been looking at expanding its chip production to other nations, with TSMC having agreed to build a plant in Arizona, while also discussing the subject with the EU. Now it looks like a deal is being worked out with India to build further chip plants there, although it's not clear who the intended manufacturer will be, as TSMC isn't mentioned in the report by Bloomberg.

However, the piece mentions 5G devices and components for electric cars, which suggests that it might not be a cutting edge node we're looking at here, but rather something a bit more conservative like 28 or 14 nm. India would make sense in many ways, but the obvious concern once again is water supply, although so far no exact location has been mentioned for the placement of the fab.

Samsung Working on Attracting more Foundry Customers by Improving Customer Structure and Process Node Breakthroughs

Samsung is by far Samsung's largest foundry customers and this is no secret, but now it seems like the company wants to gain more customers to help pay for the costs of operating a cutting edge foundry. A little over a decade ago, Samsung was part of the Common Platform technology alliance together with GlobalFoundries and IBM, which allowed companies to almost pick either foundry based on a common design kit and common process technologies. It made Samsung an attractive foundry option, but the alliance didn't last.

As we know, Nvidia gave Samsung a try with Ampere and there were a lot of reports of yield issues and what not early on. This seems to have persuaded Nvidia to move back to TSMC for Lovelace and Hopper, which is a big loss for Samsung. However, it seems this was also something of a wakeup call for Samsung, as the company is apparently looking at making some internal changes to its customer structure so it can handle third party customers in a better way.

Revenue of Top 10 IC Design (Fabless) Companies Reaches US$29.8 Billion for 2Q21, Though Growth May Potentially Slow in 2H21, Says TrendForce

In view of the ongoing production capacity shortage in the semiconductor industry and the resultant price hike of chips, revenue of the top 10 IC design companies for 2Q21 reached US$29.8 billion, a 60.8% YoY increase, according to TrendForce's latest investigations. In particular, Taiwanese companies put up remarkable performances during this period, with both MediaTek and Novatek posting YoY growths of more than 95%. AMD, on the other hand, experienced a nearly 100% YoY revenue growth, the highest among the top 10.

TrendForce indicates that the ranking of the top five companies for 2Q21 remained unchanged from the previous quarter, although there were major changes in the 6th to 10th spots. More specifically, after finalizing its acquisition of Inphi, Marvell experienced a major revenue growth and leapfrogged Xilinx and Realtek in the rankings from 9th place in 1Q21 to 7th place in 2Q21.

TSMC Rumoured to Build New Fab in Southern Taiwan

According to Nikkei, TSMC is set to start building a new fab in Kaohsiung, which is Taiwan's third largest city and located in the south of the island. It's also where ASE Technology Holding is located, which is the world's largest chip packaging and testing contractor. So far, TSMC doesn't have any fabs this far south in Taiwan, but it's not without its challenges.

The new fab is said to be designed to build chips on TSMC's 6 and 7 nm nodes, which are currently their most popular nodes, although this is likely to change as their 5 nm node begins to ramp up production. That said, there will still continue to be a huge demand for 6 and 7 nm parts, as these nodes transition to become mainstream production nodes.

ZeroPoint Technologies wants to Compress the Data in your RAM

Some of you might be old enough to remember various "RAM doubling" software software solutions that appeared back in the late 1980's for Apple, as well as in the mid 90's for Windows 95 computers. Most of them never really delivered on their claims, but now it looks like we might be getting something similar, albeit in hardware.

Swedish company ZeroPoint Technology AB has announced that it has raised €2.5 million in a seed round to bring its Ziptilion patented memory compression technology IP to the market. ZeroPoint claims a compression ratio of two to three times depending on the workload, which seems very impressive. Unlike current software compression technologies such as ZSWAP or ZRAM that are used to compress data in RAM at a rate of 1.4 to 1.5 times, ZeroPoint promises that it's hardware IP won't have any real world negative effects on system performance. In fact, they claim it'll only cause one nanosecond of extra latency when writing data and 100 nanoseconds delay when it comes to reading the compressed data from RAM.

NVIDIA Rumored to Refresh RTX 30-series with SUPER SKUs in January, RTX 40-series in Q4-2022

NVIDIA is rumored to be giving its GeForce RTX 30-series "Ampere" graphics card family a mid-term refresh by the 2022 International CES, in January; the company is also targeting Q4-2022, specifically October, to debut its next-generation RTX 40-series. The Q1 refresh will include "SUPER" branded SKUs taking over key price-points for NVIDIA, as it lands up with enough silicon that can be fully unlocked. This leak comes from Greymon55, a reliable source on NVIDIA leaks. It also aligns with the most recent pattern followed by NVIDIA to keep its GeForce product-stack updated. The company had recently released "Ti" updates to certain higher-end price-points, in response to competition from the Radeon RX 6000 "RDNA2" series.

NVIDIA's next-generation will be powered by the "Lovelace" graphics architecture that sees even more hardware acceleration for the RTX feature-set, more raytraced effects, and preparation for future APIs. It also marks NVIDIA's return to TSMC, with the architecture reportedly being designed for the 5 nm (N5) silicon fabrication node. The current-gen GeForce "Ampere" chips are being products on an 8 nm foundry node by Samsung.

Xbox Series S Refresh Rumored to Feature 6 nm AMD APU with 20+ Compute Units

Microsoft is potentially looking to refresh the Xbox Series S in late 2022 with an upgraded 6 nm AMD APU according to Moore's Law is Dead. The upgraded processor would be manufactured on TSMC's 6N process which boasts higher yields and could allow Microsoft to enable all 24 Compute Units on the APU compared to the 20 they currently enable. This increase in Compute Units and a clock speed boost could potentially increase the console's performance by 50%. This updated model would come in at close to 350 USD representing a 50 USD premium however the existing model would be retained and see a price cut to 189-249 USD. The rumor also claims that Microsoft will refresh the Xbox Series X in 2023 or later.

Foundry Revenue for 2Q21 Reaches Historical High Once Again with 6% QoQ Growth Thanks to Increased ASP and Persistent Demand, Says TrendForce

The panic buying of chips persisted in 2Q21 owing to factors such as post-pandemic demand, industry-wide shift to 5G telecom technology, geopolitical tensions, and chronic chip shortages, according to TrendForce's latest investigations. Chip demand from ODMs/OEMs remained high, as they were unable to meet shipment targets for various end-products due to the shortage of foundry capacities. In addition, wafers inputted in 1Q21 underwent a price hike and were subsequently outputted in 2Q21. Foundry revenue for the quarter reached US$24.407 billion, representing a 6.2% QoQ increase and yet another record high for the eighth consecutive quarter since 3Q19.

TSMC Raises Chip Prices by Up To 20 Percent as Chip Shortages Continue

The main supplier of advanced logic chips to the likes of Apple, Qualcomm, and AMD, among hundreds of other customers; TSMC, is reportedly planning to raise its prices by up to 20 percent, according to a report in The Wall Street Journal. The WSJ report talks about a roughly 10 percent increase in prices of logic chips built on the company's latest nodes (possibly N7 or newer); while prices of chips on older processes could rise by around 20 percent. This would have a direct impact on prices of not just PCs, but also smartphones and much of the ICT industry. The report, however, doesn't mention whether specific clients such as Apple and AMD would be affected by the new prices, as their large purchase volumes afford them bargaining power for their contracts. It will, however, wreak havoc with smaller clients that order based on demand, as well as companies planning future products.

AMD Envisions Direct Circuit Slicing for Future 3D Stacked Dies

AMD in its HotChips 33 presentation shed light on the the company's efforts to stay on the cutting edge of 3D silicon packaging technology, especially as rival Intel takes giant strides with 2.5D and 3D packaging on its latest "Ponte Vecchio" and "Sapphire Rapids" packages. The company revealed that it co-developed a pioneering new die-on-die stacking technique with TSMC for its upcoming "Zen 3" CCDs with 3D Vertical Caches, which are 64 MB SRAM dies stacked on top of "Zen 3" CCDs to serve as an extension of the 32 MB on-die L3 cache. The micro-bumps connecting the 3D Vertical Cache die with the CCD are 9-micron in pitch, compared to 10-micron on the production variant of Intel Foveros.

AMD believes that no single packaging technology works for all products, and depend entirely on what it is you're trying to stack. The company spoke on the future of die-on-die stacking. For over a decade, package-on-package stacking has been possible (as in the case of smartphones. Currently, it's possible to put memory-on-logic within a single package, between the logic die and an SRAM die for additional cache memory; a logic die an DRAM for RAM integrated with package; or even logic with NAND flash for extreme-density server devices.

Intel Xe HPG Graphics Architecture and Arc "Alchemist" GPU Detailed

It's happening, Intel is taking a very pointy stab at the AAA gaming graphics market, taking the fight to NVIDIA GeForce and AMD Radeon. The Arc "Alchemist" discrete GPU implements the Xe HPG (high performance gaming) graphics architecture, and offers full DirectX 12 Ultimate compatibility. It also offers contemporary features gamers want, such as XeSS, an AI-supersampling feature rivaling DLSS and FSR. There's a lot more to the Xe HPG architecture than being a simple a scale-up from the Xe LP-based iGPUs found in today's "Tiger Lake" processors.

Just like Compute Units on AMD GPUs, and Streaming Multiprocessors on NVIDIA, Intel designed a scalable hierarchical compute hardware structure for Xe HPG. It begins with the Xe-core, an indivisible compute building block that contains 16 each of 256-bit vector engines and 1024-bit matrix engines. combined with basic load/store hardware and an L1 cache. The vector unit here is interchangeable with the execution unit, and the Xe-core contains 16 of these. The Render Slice is a collective of four Xe-cores, four Raytracing Units; and other common fixed-function hardware that include the geometry pipeline, rasterization pipeline, samplers, and pixel-backends. The Raytracing Units contain fixed-function hardware for bounding-box intersection, ray traversal, and triangle intersection.

Intel Beats AMD to 6nm GPUs, Arc "Alchemist" Built on TSMC N6 Process

In its 2021 Architecture Day presentation, Intel revealed that its first performance gaming GPU, the Arc "Alchemist," is built on the TSMC N6 silicon fabrication node (6 nm). A more advanced node than the N7 (7 nm) used by AMD for its current RDNA2 GPUs, TSMC N6 leverages EUV (extreme ultraviolet) lithography, and offers 18% higher transistor density, besides power improvements. "With N6, TSMC provides an optimal balance of performance, density, and power-efficiency that are ideal for modern GPUs," said Dr Kevin Zhang, SVP of Business Development at TSMC.

With working prototypes of "Alchemist" already internally circulating as the "DG2," Intel has beaten AMD to 6 nm. Team Red is reportedly planning optical-shrinks of its RDNA2-based "Navi 22" and "Navi 23" chips to TSMC N6, and assigning them mid-range SKUs in the Radeon RX 7000 series. The company will build two higher-segment RDNA3 GPUs on the more advanced TSMC N5 (5 nm) process, which will release in 2022, and power successors to the RX 6700 series and RX 6800/6900 series.

Chip Shortages Could Continue Well into 2022, Predicts NVIDIA CEO Jensen Huang

In his Q2-FY2022 Results call, NVIDIA CEO Jensen Huang commented that he expects the ongoing chip supply situation to remain bad for the most part of 2022. "Meanwhile, we have and are securing pretty significant long-term supply commitments as we expand into all these different markets initiatives that we've set ourselves up for. And I so I think—I would expect that we will see a supply contained environment for the vast majority of next year is my guess at the moment," he said.

His comments are telling, as NVIDIA relies heavily on cutting edge silicon fabrication nodes for its logic products, such as GPUs, HPC processors, and vehicle SoCs. 2022 will see NVIDIA introduce its "Lovelace" graphics architecture, powering the GeForce RTX 40-series GPUs; as well as a variant powering next-generation HPC processors. The company is looking to design its chips for TSMC's 5 nm silicon fabrication process, unless Samsung can fix its 5 nm-class foundry woes in time, and win back the company.

TSMC Looking to Build a Fab in Germany

TSMC, as part of its strategy to build cutting-edge semiconductor foundries in the US and EU, is looking to build a ground-up fab in Germany. The company's chairman, Mark Liu, made an announcement to this effect in the company's annual general meeting (AGM), addressing shareholders, held on July 26. This move is still in its "early stages," according to a DigiTimes report, with the company prospecting a suitable site across the country. The size and scale of TSMC's investment remains under the wraps.

TSMC's expedition to Germany aligns with an ambitious plan by the European Commission to make the EU a net-exporter of semiconductors and electronics by 2030. TSMC will have Intel Foundry Services for company in Germany, as an acquisition of Global Foundries would put Intel in control of its real-estate in Dresden. Intel is still prospecting the EU for a suitable place to invest €20 billion, besides ongoing investments in states such as the Republic of Ireland.

Intel Rebadges 10nm Enhanced SuperFin Node as "Intel 7," Invents Other Creative Node Names

Intel, in a move comparable to its competitors' Performance Rating system from the 1990s, has invented a new naming scheme for its in-house foundry nodes to claim technological parity with contemporaries such as TSMC and Samsung, that are well into the sub-10 nm class. Back in the i586 era, when Intel's competitors such as AMD and Cyrix, couldn't keep up with its clock-speeds yet found their chips to be somewhat competitive, they invented the PR (processor rating) system, with a logical number attempting to denote parity with an Intel processor's clock-speed. For example, a PR400 processor rating meant that the chip rivaled a Pentium II 400 MHz (which it mostly didn't). The last that the PR system made sense was with the final generation of single-core performance chips, Pentium 4 and Athlon XP, beyond which, the introduction of multi-core obfuscated the PR system. A Phenom X4 9600 processor didn't mean performance on par with a rival Intel chip running at an impossible 9.60 GHz.

Intel's new foundry naming system sees its 10 nm Enhanced SuperFin node re-badge as "Intel 7." The company currently builds 11th Gen Core "Tiger Lake" processors on the 10 nm SuperFin node, and is expected to build its upcoming 12th Gen Core "Alder Lake" chips on its refinement, the 10 nm Enhanced SuperFin, which will now be referred to as "Intel 7." The company is careful to avoid using the nanometer unit next to the number, instead signaling the consumer that the node somehow offers transistor density and power characteristics comparable to a 7 nm node. Intel 7 offers a 10-15 percent performance/Watt gain over 10 nm SuperFin, and is already in volume production, with a debut within 2021 with "Alder Lake."

Next-Gen AMD Radeon RDNA3 Flagship To Feature 15,360 Stream Processors?

AMD's next generation RDNA3 graphics architecture generation could see a near-quadrupling in raw SIMD muscle over the current RDNA2, according to a spectacular rumor. Apparently, the company will deploy as many as 15,360 stream processors (quadruple that of a Radeon RX 6800), and spread across 60 WGPs (Workgroup Processors), and do away with the compute unit. This is possibly because the RDNA3 compute unit won't be as independent as the ones on the original RDNA or even RDNA2, which begins to see groups of two CUs share common resources.

Another set of rumors suggest that AMD won't play NVIDIA's game of designing GPUs with wide memory bus widths, and instead build on its Infinity Cache technology, by increasing the on-die cache size and bandwidth, while retaining "affordable" discrete memory bus widths, such as 256-bit. As for the chip itself, it's rumored that the top RDNA3 part, the so-called "Navi 31," could feature a multi-chip module design (at least two logic dies), each with 30 WGPs. Each of the two is expected to be built on a next-gen silicon fabrication node that's either TSMC N5 (5 nm), or a special 6 nm node TSMC is designing for AMD. Much like the next-generation "Lovelace" architecture by NVIDIA, AMD's RDNA3 could see the light of the day only in 2022.

NVIDIA "Ada Lovelace" Architecture Designed for N5, GeForce Returns to TSMC

NVIDIA's upcoming "Ada Lovelace" architecture, both for compute and graphics, is reportedly being designed for the 5 nanometer silicon fabrication node by TSMC. This marks NVIDIA's return to the Taiwanese foundry after its brief excursion to Samsung, with the 8 nm "Ampere" graphics architecture. "Ampere" compute dies continue to be built on TSMC 7 nm nodes. NVIDIA is looking to double the compute performance on its next-generation GPUs, with throughput approaching 70 TFLOP/s, from a numeric near-doubling in CUDA cores, generation-over-generation. These will also be run at clock speeds above 2 GHz. One can expect "Ada Lovelace" only by 2022, as TSMC N5 matures.

Valve Steam Deck SoC Detailed: AMD Brings Zen2 and RDNA2 to the Table

Valve today announced its first big splash into the console market with Steam Deck, a device out to eat the Nintendo Switch's lunch. The announcement comes as yet another feather in AMD's cap for its semi-custom SoC business, benefiting from being the only company with an x86-64 CPU license and having a cutting-edge graphics hardware IP. Built on the 7 nm node at TSMC, the semi-custom chip at the heart of the Steam Deck is designed for extended gameplay on battery, and is a monolithic silicon that combines CPU, GPU, and core-logic.

The yet-unnamed semi-custom chip features a 4-core/8-thread CPU based on the "Zen 2" microarchitecture, with a nominal clock speed of 2.40 GHz, and up to 3.50 GHz boost. The CPU component offers an FP32 throughput of 448 GFLOP/s. The GPU is based on AMD's latest RDNA2 graphics architecture—the same one powering the Xbox Series X, PlayStation 5, and Radeon RX 6900 XT—and is comprised of 8 RDNA2 compute units (512 stream processors). The GPU operates at an engine clock speed of 1.10 GHz to 1.60 GHz, with peak compute power of 1.6 TFLOP/s. The silicon uses a unified memory interface, and a cutting-edge LPDDR5 memory controller.
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