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TSMC Said to be Eyeing Singapore for Fab Expansion

The rumour mill never seems to stop churning when it comes to TSMC and now the company is said to be looking at the tiny nation of Singapore for a future fab. This time the information comes via the Wall Street Journal rather than the usual Taiwanese sources and although the publication points out that no decision has been made at this point in time, it says that TSMC is apparently in talks with the Economic Development Board of Singapore. The official statement from the TSMC on the matter is that the company "doesn't rule out any possibility but does not have any concrete plan at this time".

The potential Singapore Fab would be producing 28 to 7 nm chips, in other words, quite far from TSMC's cutting edge nodes. However, TSMC is already building a similar facility in the southern city of Kaohsiung in Taiwan that's scheduled for opening in 2024. As such, the nodes used in a future facility in Singapore might change depending on when the fab will open and it might end up producing chips on more advanced nodes as well. As these fabs take a few years to get going, they're not projects that are started on a whim. We should also mention that TSMC already has a joint venture in Singapore together with NXP, called SSMC, which also produces for third parties.

NVIDIA Releases Security Update 473.47 WHQL Driver for Kepler GPUs

Ten years ago, in 2012, NVIDIA introduced its Kepler series of graphics cards based on the TSMC 28 nm node. Architecture has been supported for quite a while now by NVIDIA's drivers, and the last series to carry support was the 470 driver class. Today, NVIDIA pushed a security update in the form of a 473.47 WHQL driver that brings fixes to various CVE vulnerabilities that can cause anything from issues that may lead to denial of service, information disclosure, or data tampering. This driver version has no fixed matters and doesn't bring any additional features except the fix for vulnerabilities. With CVEs rated from 4.1 to 8.5, NVIDIA has fixed major issues bugging Kepler GPU users. With a high risk for code execution, denial of service, escalation of privileges, information disclosure, and data tampering, the 473.47 WHQL driver is another step for supporting Kepler architecture until 2024, when NVIDIA plans to drop the support for this architecture. Supported cards are GT 600, GT 700, GTX 600, GTX 700, Titan, Titan Black, and Titan Z.

The updated drivers are available for installation on NVIDIA's website and for users of TechPowerUp's NVCleanstall software.

NVIDIA GeForce RTX 4090 Twice as Fast as RTX 3090, Features 16128 CUDA Cores and 450W TDP

NVIDIA's next-generation GeForce RTX 40 series of graphics cards, codenamed Ada Lovelace, is shaping up to be a powerful graphics card lineup. Allegedly, we can expect to see a mid-July launch of NVIDIA's newest gaming offerings, where customers can expect some impressive performance. According to a reliable hardware leaker, kopite7kimi, NVIDIA GeForce RTX 4090 graphics card will feature AD102-300 GPU SKU. This model is equipped with 126 Streaming Multiprocessors (SMs), which brings the total number of FP32 CUDA cores to 16128. Compared to the full AD102 GPU with 144 SMs, this leads us to think that there will be an RTX 4090 Ti model following up later as well.

Paired with 24 GB of 21 Gbps GDDR6X memory, the RTX 4090 graphics card has a TDP of 450 Watts. While this number may appear as a very power-hungry design, bear in mind that the targeted performance improvement over the previous RTX 3090 model is expected to be a two-fold scale. Paired with TSMC's new N4 node and new architecture design, performance scaling should follow at the cost of higher TDPs. These claims are yet to be validated by real-world benchmarks of independent tech media, so please take all of this information with a grain of salt and wait for TechPowerUp reviews once the card arrives.

Intel "Meteor Lake" 2P+8E Silicon Annotated

Le Comptoir du Hardware scored a die-shot of a 2P+8E core variant of the "Meteor Lake" compute tile, and Locuza annotated it. "Meteor Lake" will be Intel's first processor to implement the company's IDM 2.0 strategy to the fullest. The processor is a multi-chip module of various tiles (chiplets), each with a certain function, sitting on die made on a silicon fabrication node most suitable to that function. Under this strategy, for example, if Intel's chip-designers calculate that the iGPU will be the most power-hungry component on the processor, followed by the CPU cores, the graphics tile will be built on a more advanced process than the compute tile. Intel's "Meteor Lake" and "Arrow Lake" processors will implement chiplets built on the Intel 4, TSMC N3, and Intel 20A fabrication nodes, each with unique power and transistor-density characteristics. Learn more about the "Meteor Lake" MCM in our older article.

The 2P+8E (2 performance cores + 8 efficiency cores) compute tile is one among many variants of compute tiles Intel will develop for the various SKUs making up the next-generation Core mobile processor series. The die is annotated with the two large "Redwood Cove" P-cores and their cache slices taking up about 35% of the die area; and the two "Crestmount" E-core clusters (each with 4 E-cores), and their cache slices, taking up the rest. The two P-cores and two E-core clusters are interconnected by a Ring Bus, and share an L3 cache. The size of each L3 cache slice is either 2.5 MB or 3 MB. At 2.5 MB, the total L3 cache will be 10 MB, and at 3 MB, it will be 12 MB. As with all past generations, the L3 cache is fully accessible by all CPU cores in the compute tile.

TSMC Said to be Planning Price Increases in 2023

The global inflation rises are no secret and more and more companies are looking to increase prices of their goods, so not entirely unsurprising, reports of TSMC planning price hikes in early 2023 are starting to appear. TSMC has supposedly already contacted its customers to notify them about the upcoming price increase, to give them as much time as possible to make any changes to their plans, if needed. The price increase will vary depending on the node in question, but is reported to be somewhere between five and eight percent according to the Nikkei.

Part of the increase is also related to TSMC's rapid expansion that's going on at the moment, since the company is going to need to invest a lot more capital when it comes to building the advanced fabs that its customers are relying on. TSMC is expected to invest some US$40-44 billion this year alone on fabs and new equipment. This is a fairly small price increase compared to the big increase TSMC implemented in August 2021, where some nodes saw price hikes of up to 20 percent. That said, TSMC isn't alone in increasing their pricing, as UMC and SMIC have also increased their prices several times since last year. Nikkei claims that UMC and SMIC are charging more than TSMC on some nodes. However, in the past, TSMC used to offer discounts to its clients on a quarterly basis once a chip had gone into mass production and everything progressed smoothly, but TSMC discontinued this discount scheme last year. As such, it looks like cheaper chip costs aren't to be expected any time soon.

AMD Ryzen 7000U "Phoenix" Processor iGPU Matches RTX 3060 Laptop GPU Performance: Rumor

AMD is planning a massive integrated graphics performance uplift for its next-generation Ryzen 7000U mobile processors. Codenamed "Phoenix," this SoC will feature a CPU based on the "Zen 4" microarchitecture with a higher CPU core count than the Intel alternative of the time; and an iGPU based on the RDNA3 graphics architecture. AMD is planning to endow this with the right combination of a CU count and engine clocks, to result in performance that roughly matches the NVIDIA GeForce RTX 3060 Laptop GPU, a popular performance-segment discrete GPU for notebooks, according to greymon55. Other highlights of "Phoenix" include a DDR5 + LPDDR5 memory interface, and PCI-Express Gen 5. The SoC is expected to be built on the TSMC N5 (5 nm) process, and debut in 2023.

NVIDIA H100 SXM Hopper GPU Pictured Up Close

ServeTheHome, a tech media outlet focused on everything server/enterprise, posted an exclusive set of photos of NVIDIA's latest H100 "Hopper" accelerator. Being the fastest GPU NVIDIA ever created, H100 is made on TSMC's 4 nm manufacturing process and features over 80 billion transistors on an 814 mm² CoWoS package designed by TSMC. Complementing the massive die, we have 80 GB of HBM3 memory that sits close to the die. Pictured below, we have an SXM5 H100 module packed with VRM and power regulation. Given that the rated TDP for this GPU is 700 Watts, power regulation is a serious concern and NVIDIA managed to keep it in check.

On the back of the card, we see one short and one longer mezzanine connector that acts as a power delivery connector, different from the previous A100 GPU layout. This board model is labeled PG520 and is very close to the official renders that NVIDIA supplied us with on launch day.

NVIDIA Hopper Whitepaper Reveals Key Specs of Monstrous Compute Processor

The NVIDIA GH100 silicon powering the next-generation NVIDIA H100 compute processor is a monstrosity on paper, with an NVIDIA whitepaper published over the weekend revealing its key specifications. NVIDIA is tapping into the most advanced silicon fabrication node currently available from TSMC to build the compute die, which is TSMC N4 (4 nm-class EUV). The H100 features a monolithic silicon surrounded by up to six on-package HBM3 stacks.

The GH100 compute die is built on the 4 nm EUV process, and has a monstrous transistor-count of 80 billion, a nearly 50% increase over the GA100. Interestingly though, at 814 mm², the die-area of the GH100 is less than that of the GA100, with its 826 mm² die built on the 7 nm DUV (TSMC N7) node, all thanks to the transistor-density gains of the 4 nm node over the 7 nm one.

NVIDIA AD102 and AMD Navi 31 in a Race to Reach 100 TFLOPs FP32 First

A technological race is brewing between NVIDIA and AMD over which brand's GPU reaches the 100 TFLOP/s peak FP32 throughput mark first. AMD's TeraScale graphics architecture and the "RV770" silicon, were the first to hit the 1 TFLOP/s mark, way back in 2008. It would take 14 years for this figure to reach 100 TFLOP/s for flagship GPUs. NVIDIA's next generation big GPU based on the "Ada Lovelace," the AD102, is the green team's contender for the 100 TFLOP/s mark, according to kopite7kimi. To achieve this, all 144 streaming multiprocessors (SM) or 18,432 CUDA cores, of the AD102 will have to be enabled.

From the red team, the biggest GPU based on the next-generation RDNA3 graphics architecture, "Navi 31," could offer peak FP32 throughput of 92 TFLOP/s according to greymon55, which gives AMD the freedom to create special SKUs running at high engine clocks, just to reach the 100 TFLOP/s mark. The Navi 31 silicon is expected to triple the compute unit count over its predecessor, resulting in 15,360 stream processors. Both the AD102 and Navi 31 are expected to be built on the same TSMC N5 (5 nm EUV) node, and product launches for both are expected by year-end.

AMD MI300 Compute Accelerator Allegedly Features Eight Logic Dies

AMD's next-generation MI300 compute accelerator is expected to significantly scale up the logic density, according to a rumor by Moore's Law is Dead. Based on the CDNA3 compute architecture, the MI300 will be a monstrous large multi-chip module with as many as 8 logic dies (compute dies), each with its dedicated HBM3 stack. The compute dies (logic dies), will be 3D-stacked on top of I/O dies that pack the memory controllers, and the interconnect that performs the inter-die, and inter-package communication.

The report even goes on to mention that the compute die at the top level of the stack will be built on TSMC N5 (5 nm) silicon fabrication process, while the I/O die below will be TSMC N6 (6 nm). At this point it's not known if AMD will use the package to wire the logic stacks to the memory stacks, or whether it will take the pricier route of using a silicon interposer, but the report supports the interposer theory—that an all-encompassing interposer seats all eight compute dies, all four I/O dies (each with two compute dies), and the eight HBM3 stacks. An interposer is a silicon die that facilitates high density microscopic wiring between two dies on a package, which are otherwise not possible through large package substrate wiring.

India is Pitching Itself as the Next Semiconductor Fab Location to Intel, GlobalFoundries and TSMC

At the end of 2021, there was quite a lot of noise when it came to India's homegrown semiconductor fab initiative, where the nation was trying to win over Intel, as well as some other semiconductor manufacturers. It would appear that the Indian government has stepped up its efforts and is now actively pitching to Intel, GlobalFoundries and TSMC. The main person behind this is said to be Rajeev Chandrasekhar, the minister of state for technology and entrepreneurship and a former Intel engineer. So far it seems like Chandrasekhar hasn't gotten very far according to the article The Economic Times, where he states that "We're meeting the CEOs, talking to them, making presentations."

On the other hand, recent news has suggested that Foxconn is interested in setting up some kind of foundry in India, in a partnership with local Vedanta Group. It's unclear what kind of semiconductors this would be for though, especially as Vedanta is mostly in the mining industry. The various Indian states are said to be very keen on the other hand, both in terms of getting new industry, but also in getting new investments. Earlier this month, during his tour of several Asian countries, Intel's CEO, Pat Gelsinger had a meeting with the Indian Prime Minister, Narendra Modi, but what came of that meeting is unclear. India is hoping to be able to reproduce the success it has had when it comes to manufacturing smartphones locally, with Samsung, Nokia and Xiaomi producing locally, as well as Taiwanese Foxconn, Wistron and Pegatron, who contract manufacture Apple devices. However, semiconductors are far more complex to make than smartphones, so if India isn't willing to play the long game, it's unlikely much will come of its attempts to attract semiconductor foundries.

Localization of Chip Manufacturing Rising; Taiwan to Control 48% of Global Foundry Capacity in 2022, Says TrendForce

According to TrendForce, Taiwan is crucial to the global semiconductor supply chain, accounting for a 26% market share of semiconductor revenue in 2021, ranking second in the world. Its IC design and packaging & testing industries also account for a 27% and 20% global market share, ranking second and first in the world, respectively. Firmly in the pole position, Taiwan accounts for 64% of the foundry market. In addition to TSMC possessing the most advanced process technology at this stage, foundries including UMC, Vanguard, and PSMC also have their own process advantages. Under the looming shadow of chip shortages caused by the pandemic and geopolitical turmoil in the past two years, various governments have quickly awakened to the fact that localization of chip manufacturing is necessary to avoid being cut off from chip acquisition due to logistics difficulties or cross-border shipment bans. Taiwanese companies have ridden this wave to become partners that governments around the world are eager to invite to set up factories in various locales.

Apple, Intel to Become Alpha Customers for TSMC's 2 nm Manufacturing Node

Industry reports and sources in the financial community have placed Apple and Intel as the two premier customers for TSMC's upcoming N2 node. N2, which is expected to enter volume production by the end of 2025, will be TSMC's first manufacturing process making use of GAAFET (Gate-All-Around Field-Effect Transistor) design. If there are no significant market upheavals or unexpected snags in technology transition, TSMC will be late to the GAAFET party, following Samsung's 3GAE node in 2023 and Intel's first Angstrom-era process, Intel 20A, in 2024.

While Apple's uptake on TSMC's latest manufacturing technology is practically a given at this point, the fact that Intel too is taking up TSMC's N2 node showcases the company's evolved business tactics after the introduction of its IDM 2.0 strategy (IDM standing for Integrated Device Manufacturer, meaning Intel too will fabricate chips according to clients' specs). While pre-Pat Gelsinger was seemingly scared of touching any other foundries' products - mostly from the fact that Intel does have its own significant manufacturing capabilities and R&D, after all - the new Intel is clearly more at peace with driving its competitor's revenues.

TSMC Founder Says Growing Domestic US Chip Production is Wasteful and Expensive

According to an article over on The Register, the TSMC founder, Morris Chang, isn't overly impressed by US efforts to grow its domestic chip production. In a podcast hosted by the Brookings Institution, Morris Chang said that the US' attempt to grow its domestic chip production will be "a wasteful, expensive exercise in futility." The reason behind his comment is that he believes the US is lacking the talent to work in the fabs, or possibly the willingness to work triple-shift to keep the fabs running 24/7, unlike the Taiwanese. Furthermore, he states that the US can't compete in terms of cost, as he claims it's 50 percent more expensive to manufacture chips in the US compared to Taiwan.

It should be pointed out that Morris Chang is no longer involved with the day to day operations at TSMC and the above are just his opinion. When questioned about why TSMC is building a fab in Arizona, Chang said that TSMC decided to do it because they were urged to do so by the US government. He also believes that despite government subsidies, the US is unlikely to become self-sufficient when it comes to semiconductors, especially as the cost per chip will be much higher, which will make it hard to compete internationally. However, he does mention that if the PRC decided to start a war with Taiwan, then the bet is likely to pay off for the US, but there are obviously other problems that such a situation would bring as well. Chang also praises US chip design talent and says that Taiwan has very little talent in comparison and that TSMC has none. However, the latter doesn't seem to be entirely true, based on the fact that TSMC is helping its customers to optimise their designs for the various production nodes at TSMC. For those interested, the podcast can be found below.

AMD Radeon RX 6400 Launched at $159

AMD formally launched the entry-level Radeon RX 6400 graphics card. At an MSRP of $159, this is the most affordable graphics card from the Radeon RX 6000 series. It is based on the same RDNA2 graphics architecture as the rest of the RX 6000 lineup, and the smallest silicon of them all, the "Navi 23." This chip is built on the TSMC N6 (6 nm) silicon fabrication process.

The RX 6400 shares the "Navi 23" silicon with the RX 6500 XT launched earlier this year. AMD enabled 12 out of 16 RDNA2 compute units on the silicon, resulting in 768 stream processors, 48 TMUs, 12 Ray Accelerators, and 32 ROPs. The memory configuration is similar to the RX 6500 XT, with 4 GB of GDDR6 memory across a 64-bit wide memory bus. This is the same 16 Gbps-rated memory, which means 128 GB/s bandwidth on tap. There's also 16 MB of Infinity Cache. The engine clocks (GPU clocks) are set at 2039 MHz (game) and 2321 MHz (boost). With its given specs, the RX 6400 has a typical graphics power (TGP) of just 53 W, and so cards can do without any power connectors.

PowerColor Radeon RX 6650 XT Hellhound Specs Sheet Hints at Clock Speed Increases Over RX 6600 XT

A leaked specifications sheet of the upcoming PowerColor Radeon RX 6650 XT Hellhound custom-design graphics card, seen by VideoCards, sheds light on AMD's play at carving out the RX 6650 XT. It involves dialing up the engine clocks (GPU clock speed), and memory bandwidth. At this point it is not known if the RX 6650 XT is based on a refined variant of the "Navi 23" silicon, possibly leveraging the TSMC N6 (6 nm) process, or if it's just a case of AMD dialing up clock speeds while pushing up the typical board power, on existing 7 nm (TSMC N7) process.

The RX 6650 XT Hellhound comes with about 4.3% increase in game clocks in its default "OC mode" BIOS, and about 3.7% increase in maximum boost clocks, up from 2593 MHz to 2689 MHz. The "Silent mode" BIOS of the RX 6650 XT Hellhound offers better clock speeds than the "OC mode" BIOS of the RX 6600 XT Hellhound, at 2410 MHz game, 2635 MHz boost, compared to 2382 MHz game, 2593 MHz boost. The other big surprise is memory clocks, with AMD possibly using 17.5 Gbps GDDR6 memory speeds, compared to 16 Gbps on the RX 6600 XT. This results in a 9.4% increase in memory bandwidth. The RX 6600 XT Hellhound uses a single 8-pin PCIe power connector, for an input capacity of 225 W (including the PCIe slot power), which is sufficient for the card's 160 W typical board power. The TBP of the RX 6650 XT Hellhound is not known, but given that its specs sheet still shows single 8-pin, it has to be under 225 W.

TSMC to Start 2 nm Production by 2025, 3 nm by the End of 2022

Responding to investor questions in TSMC's first quarter earnings call for 2022, CEO C. C. Wei reiterated that the company's upcoming manufacturing processes are generally moving smoothly throughout development. Even as TSMC announced historic revenues on the back of increased pricing throughout the semiconductor industry, the company is showing no signs of slowing down on its development. When further asked regarding the company's ability to navigate the world's troubled, inflation-ridden waters, Wei added that TSMC's strategic positioning as the leading semiconductor foundry makes it resilient to market and demand fluctuations.

TSMC's roadmap has seen multiple accelerations of late, which have placed 3 nm tape-out to occur before the end of the year. Perhaps more significantly, the company's next-generation 2 nm manufacturing process, which will make use of GAA (Gate All Around) transistor designs for greater design efficiency and density, are still on track for a 2025 volume production following an expected 2024 tape-out.

Alibaba Previews Home-Grown CPUs with 128 Armv9 Cores, DDR5, and PCIe 5.0 Technology

One of the largest cloud providers in China, Alibaba, has today announced a preview for a new instance powered by Yitian 710 processor. The new processor is a collection of Alibaba's efforts to develop a home-grown design capable of powering cloud instances and the infrastructure needed for it and its clients. Without much further ado, the Yitian 710 is based on Armv9 ISA and features 128 cores. Ramping up to 3.2 GHz, these cores are paired with eight-channel DDR5 memory to enable sufficient data transfer. In addition, the CPU supports 96 PCIe 5.0 lanes for IO with storage and accelerators. These are most likely custom designs, and we don't know if they are using a blueprint based on Arm's Neoverse. The CPU is manufactured at TSMC's facilities on 5 nm node and features 60 billion transistors.

Alibaba offers these processors as a part of their Elastic Compute Service (ECS) instance called g8m, where users can select 1/2/4/8/16/32/64/128 vCPUs, where each vCPU is equal to one CPU core physically. Alibaba is running this as a trial option and notes that users should not run production code on these instances, as they will disappear after two months. Only 100 instances are available for now, and they are based in Alibaba's Hangzhou zone in China. The company notes that instances based on Yitian 710 processors offer 100 percent higher efficiency than existing AMD/Intel solutions; however, they don't have any useful data to back it up. The Chinese cloud giant is likely trying to test and see if the home-grown hardware can satisfy the needs of its clients so that they can continue the path to self-sustainability.

TSMC First Quarter 2022 Financials Show 45.1% Increase in Revenues

A new quarter and another forecast shattering revenue report from TSMC, as the company beat analysts' forecasts by over US$658 million, with a total revenue for the quarter of US$17.6 billion and a net income of almost US$7.26 billion. That's an increase in net income of 45.1 percent or 35.5 percent in sales. Although the monetary figures might be interesting to some, far more interesting details were also shared, such as production updates about future nodes. As a followup on yesterday's news post about 3 nanometer nodes, the N3 node is officially on track for mass production in the second half of this year. TSMC says that customer engagement is stronger than at the start of its N7 and N7 nodes, with HPC and smartphone chip makers lining up to get onboard. The N3E node is, as reported yesterday, expected to enter mass production in the second half of 2023, or a year after N3. Finally, the N2 node is expected in 2025 and won't adhere to TSMC's two year process technology cadence.

Breaking down the revenue by nodes, N7 has taken back the lead over N5, as N7 accounted for 30 percent of TSMC's Q1 revenues up from 27 percent last quarter, but down from 35 percent in the previous year. N5 sits at 20 percent, which is down from 23 percent in the previous quarter, but up from 14 percent a year ago. The 16 and 28 nm nodes still hold on to 25 percent of TSMC's revenue, which is the same as a year ago and up slightly from the previous quarter. Remaining nodes are unchanged from last quarter.

TSMC's N3E Node Said to Have Good Yields, Volume Production Expected Q2 2023

Back in March there were reports of TSMC's N3E node having been moved from 2024 to the end of 2023. However, it seems like the node is already seeing better than expected yields and is now being pulled in further and TSMC is expecting to start volume production as early as Q2 in 2023. The node does appear to have been frozen when it comes to further development as of the end of March. Yields are said to be much higher than the N3B node, which is also under development, but with limited information available about it.

The first customer for the new node is expected to be Apple, as the company is largely paying for much of the cutting edge node development at TSMC. However, both Intel and Qualcomm are said to be some of the first customers for the new node. More details should hopefully be announced tomorrow during TSMC's first quarter earnings call. The N3E node is a reduced layer EUV process, but before it goes into mass production, it's likely we'll be seeing the N3 node first. Early production of 3 nm parts later this year is expected to be at around 10 to 20k wafers per month initially, rising to about 25 to 35k a month once TSMC's new fab is ready. Once the N3E node is in full swing, the monthly capacity of 3 nm parts should be around 50k wafers a month, but depending on customer demand, it might end up being even higher.

"Navi 31" RDNA3 Sees AMD Double Down on Chiplets: As Many as 7

Way back in January 2021, we heard a spectacular rumor about "Navi 31," the next-generation big GPU by AMD, being the company's first logic-MCM GPU (a GPU with more than one logic die). The company has a legacy of MCM GPUs, but those have been a single logic die surrounded by memory stacks. The RDNA3 graphics architecture that the "Navi 31" is based on, sees AMD fragment the logic die into smaller chiplets, with the goal of ensuring that only those specific components that benefit from the TSMC N5 node (6 nm), such as the number crunching machinery, are built on the node, while ancillary components, such as memory controllers, display controllers, or even media accelerators, are confined to chiplets built on an older node, such as the TSMC N6 (6 nm). AMD had taken this approach with its EPYC and Ryzen processors, where the chiplets with the CPU cores got the better node, and the other logic components got an older one.

Greymon55 predicts an interesting division of labor on the "Navi 31" MCM. Apparently, the number-crunching machinery is spread across two GCD (Graphics Complex Dies?). These dies pack the Shader Engines with their RDNA3 compute units (CU), Command Processor, Geometry Processor, Asynchronous Compute Engines (ACEs), Rendering Backends, etc. These are things that can benefit from the advanced 5 nm node, enabling AMD to the CUs at higher engine clocks. There's also sound logic behind building a big GPU with two such GCDs instead of a single large GCD, as smaller GPUs can be made with a single such GCD (exactly why we have two 8-core chiplets making up a 16-core Ryzen processors, and the one of these being used to create 8-core and 6-core SKUs). The smaller GCD would result in better yields per wafer, and minimize the need for separate wafer orders for a larger die (such as in the case of the Navi 21).

AMD EPYC "Genoa" Zen 4 Processor Multi-Chip Module Pictured

Here is the first picture of a next-generation AMD EPYC "Genoa" processor with its integrated heatspreader (IHS) removed. This is also possibly the first picture of a "Zen 4" CPU Complex Die (CCD). The picture reveals as many as twelve CCDs, and a large sIOD silicon. The "Zen 4" CCDs, built on the TSMC N5 (5 nm EUV) process, look visibly similar in size to the "Zen 3" CCDs built on the N7 (7 nm) process, which means the CCD's transistor count could be significantly higher, given the transistor-density gained from the 5 nm node. Besides more number-crunching machinery on the CPU core, we're hearing that AMD will increase cache sizes, particularly the dedicated L2 cache size, which is expected to be 1 MB per core, doubling from the previous generations of the "Zen" microarchitecture.

Each "Zen 4" CCD is reported to be about 8 mm² smaller in die-area than the "Zen 3" CCD, or about 10% smaller. What's interesting, though, is that the sIOD (server I/O die) is smaller in size, too, estimated to measure 397 mm², compared to the 416 mm² of the "Rome" and "Milan" sIOD. This is good reason to believe that AMD has switched over to a newer foundry process, such as the TSMC N7 (7 nm), to build the sIOD. The current-gen sIOD is built on Global Foundries 12LPP (12 nm). Supporting this theory is the fact that the "Genoa" sIOD has a 50% wider memory I/O (12-channel DDR5), 50% more IFOP ports (Infinity Fabric over package) to interconnect with the CCDs, and the mere fact that PCI-Express 5.0 and DDR5 switching fabric and SerDes (serializer/deserializers), may have higher TDP; which together compel AMD to use a smaller node such as 7 nm, for the sIOD. AMD is expected to debut the EPYC "Genoa" enterprise processors in the second half of 2022.

AMD Claims Radeon RX 6500M is Faster Than Intel Arc A370M Graphics

A few days ago, Intel announced its first official discrete graphics card efforts, designed for laptops. Called the Arc Alchemist lineup, Intel has designed these SKUs to provide entry-level to high-end options covering a wide range of use cases. Today, AMD has responded with a rather exciting Tweet made by the company's @Radeon Twitter account. The company compared Intel's Arc Alchemist A370M GPU with AMD's Radeon RX 6500M mobile SKUs in the post. These GPUs are made on TSMC's N6 node, feature 4 GB GDDR6 64-bit memory, 1024 FP32 cores, and have the same configurable TDP range of 35-50 Watts.

Below, you can see AMD's benchmarks of the following select games: Hitman 3, Total War Saga: Troy, F1 2021, Strange Brigade (High), and Final Fantasy XIV. The Radeon RX 6500M GPU manages to win in all of these games, thus explaining AMD's "FTW" hashtag on Twitter. Remember that these are vendor-supplied benchmarks runs, so we have to wait for some media results to surface.

Intel Arc DG2-512 Built on TSMC 6nm, Has More Transistors than GA104 and Navi 22

Some interesting technical specifications of the elusive two GPUs behind the Intel Arc "Alchemist" series surfaced. The larger DG2-512 silicon in particular, which forms the base for the Arc 5 and Arc 7 series, is interesting, in that it is larger in every way than the performance-segment ASICs from both NVIDIA and AMD. The table below compares the physical specs of the DG2-512, with the NVIDIA GA104, and the AMD Navi 22. This segment of GPUs has fairly powerful use-cases, including native 1440p gameplay, or playing at 4K with a performance enhancement—something Intel has, in the form of the XeSS.

The DG2-512 is built on the 6 nm TSMC N6 foundry node, the most advanced node among the three GPUs in this class. It has the highest transistor density of 53.4 mTr/mm², and the largest die-area of 406 mm², and the highest transistor-count of 21.7 billion. The Xe-HPG graphics architecture is designed for full DirectX 12 Ultimate feature support, and the DG2-512 dedicated hardware for ray tracing, as well as AI acceleration. The Arc A770M is the fastest product based on this silicon, however, it is a mobile GPU with aggressive power-management characteristic to the form-factor it serves. Here, the DG2-512 has an FP32 throughput of 13.5 TFLOPs, compared to 13.2 TFLOPs of the Navi 22 on the Radeon RX 6700 XT desktop graphics card, and the 21.7 TFLOPs of the GA104 that's maxed out on the GeForce RTX 3070 Ti desktop graphics card.

AMD Ryzen 7000 "Raphael" Zen 4 Processors Enter Mass-Production by April-May?

The next-generation AMD Ryzen 7000 "Raphael" desktop processors in the Socket AM5 package are rumored to enter mass-production soon, according to Greymon55 on Twitter, a reliable source with AMD leaks. Silicon fabrication of the chips may already be underway, as the source claims that packaging (placing the dies on the fiberglass substrate or package), will commence by late-April or early-May. "Raphael" is a multi-chip module of "Zen 4" CCDs fabricated on the TSMC N5 (5 nm) node, combined with a cIOD built on a yet-unknown node. A plant in China performs packaging.

It's hard to predict retail availability, but for the Ryzen 5000 "Vermeer" processors, this development milestone was reached in June 2020, with the first products hitting shelves 4 months later, in November. This was, however, in the thick of the pre-vaccine COVID-19 pandemic. The "Zen 4" CPU cores are expected to introduce an IPC increase, as well as higher clock speeds. Also on offer will be next-gen connectivity, including PCI-Express Gen 5 (including CPU-attached Gen 5 NVMe), and DDR5 memory. These processors will launch alongside Socket AM5 motherboards based on the new AMD 600 series chipsets.
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